Attention is currently required from: Intel coreboot Reviewers, Matt DeVillier, Sean Rhodes.
Hello Intel coreboot Reviewers, Sean Rhodes, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/87486?usp=email
to look at the new patch set (#3).
Change subject: soc/intel/apollolake/acpi: Add function to get PCIe BAR ......................................................................
soc/intel/apollolake/acpi: Add function to get PCIe BAR
Commit 12abfb43dc0a ("soc/intel/cnvi: Add CNVW OpRegion") added an ACPI function call to _SB_.PCI0.GPCB(), which is present in the SoC common northbridge.asl, but not in the Apollolake northbridge.asl.
Add the missing GPCB function to the APL northbridge. Per Intel doc 336561, the PCIEXBAR starts at bit 28 vs 26 on other platforms.
TEST=build/boot google/ampton, verify no ACPI errors in dmesg related to missing function/object, Windows boots without BSOD.
Change-Id: Ib45d655a30bf68e9b3d24a444c505e515c4950a6 Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/soc/intel/apollolake/acpi/northbridge.asl 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/87486/3