Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Julius Werner, build bot (Jenkins), Patrick Georgi, Vanny E, Huang Jin, Lee Leahy, Damien Zammit, David Guckian, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34752
to look at the new patch set (#10).
Change subject: arch/x86: Attempt to boot without postcar stage/phase ......................................................................
arch/x86: Attempt to boot without postcar stage/phase
This patch provides option for soc to exclude postcar (!RAMSTAGE_LOADS_FROM_ROMSTAGE) stage to avoid an additional stage loading and executing time. This effort has 2 benefits:
1. Save boot time by ~4ms 2. Avoid generation of postcar.elf which saves (25kB * 3copies = 75kB) of SPI footprint.
By current design the postcar stage/phase handles the cache-as-ram tear down and as cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer in ramstage (similar to postcar) to perform below operations:
1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage.
Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the ramstage stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction.
With this CL, we will have 2 possible approach to load ramstage 1. romstage -> postcar -> ramstage Referred as RAMSTAGE_LOADS_FROM_POSTCAR (majority of x86 platform selected this from Kconfig)
2. romstage -> ramstage Referred as RAMSTAGE_LOADS_FROM_ROMSTAGE (additional option to load ramstage without introducing intermediate postcar stage)
Change-Id: Ibc88e6727b2fa692585dffe576e69f6d4d0b349d Credit-to: Aaron Durbin adurbin@chromium.org Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/Kconfig M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc M src/arch/x86/c_start.S M src/arch/x86/exit_car.S M src/lib/program.ld M src/soc/intel/common/block/cpu/Makefile.inc 7 files changed, 54 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/34752/10