[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Set correct serirq mode

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded a new patch set (#5) to the change originally created by Jeremy Soller. ( https://review.coreboot.org/c/coreboot/+/31536 )

Change subject: soc/intel/cannonlake: Set correct serirq mode
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soc/intel/cannonlake: Set correct serirq mode

Set FSP params PchSirqEnable/PchSirqMode based on board
setting of serirq_mode. Matches implementation on Skylake.

This is a no-change for existing boards since the default
remains SERIRQ_QUIET mode.

Tested on system76 galp3-c, out-of-tree WHL-U board

Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59
Signed-off-by: Jeremy Soller 
Signed-off-by: Matt DeVillier 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/lpc.c
3 files changed, 10 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31536/5