[coreboot-gerrit] Change in coreboot[master]: include/console: Rename and update POST_ENTRY_RAMSTAGE postcode

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52947 )

Change subject: include/console: Rename and update POST_ENTRY_RAMSTAGE postcode
......................................................................

include/console: Rename and update POST_ENTRY_RAMSTAGE postcode

Rename and update POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f
to make the ramstage postcodes appear in an incremental order.

Signed-off-by: Subrata Banik 
Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52947
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Marshall Dawson 
---
M src/include/console/post_codes.h
M src/lib/hardwaremain.c
2 files changed, 9 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Marshall Dawson: Looks good to me, approved

diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 9682e4d..9b2398c 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -112,6 +112,14 @@
 #define POST_PRE_HARDWAREMAIN			0x6e

/**
+ * \brief Entry into coreboot in RAM stage main()
+ *
+ * This is the first call in hardwaremain.c. If this code is POSTed, then
+ * ramstage has successfully loaded and started executing.
+ */
+#define POST_ENTRY_HARDWAREMAIN			0x6f
+
+/**
  * \brief Before Device Probe
  *
  * Boot State Machine: bs_pre_device()
@@ -196,14 +204,6 @@
 #define POST_BS_PAYLOAD_BOOT			0x7b

/**
- * \brief Entry into coreboot in RAM stage main()
- *
- * This is the first call in hardwaremain.c. If this code is POSTed, then
- * ramstage has successfully loaded and started executing.
- */
-#define POST_ENTRY_RAMSTAGE                     0x80
-
-/**
  * \brief Before calling FSP Notify before End of Firmware
  *
  * Going to call into FSP binary for Notify phase
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index 895a942..cd4a57e 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -442,7 +442,7 @@
    cbmem_initialize();

timestamp_add_now(TS_START_RAMSTAGE);
-	post_code(POST_ENTRY_RAMSTAGE);
+	post_code(POST_ENTRY_HARDWAREMAIN);

/* Handoff sleep type from romstage. */
    acpi_is_wakeup_s3();