Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36627 )
Change subject: soc/intel/icelake: Move pch_early_init from bootblock to romstage
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Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36627/2/src/soc/intel/icelake/romst...
File src/soc/intel/icelake/romstage/pch.c:
https://review.coreboot.org/c/coreboot/+/36627/2/src/soc/intel/icelake/romst...
PS2, Line 85: pmc_gpe_init
yes, no issue
How are TPM interrupts working with this change? I would not expect the interrupt status to update at all since GPE routing wouldn't be set.
https://review.coreboot.org/c/coreboot/+/36627/2/src/soc/intel/icelake/romst...
PS2, Line 87: enable_rtc_upper_bank
i believe this is valid because vboot might use cmos during verstage while creating vboot_buffer. […]
Probably because it lives in lower bank?
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