Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42289 )
Change subject: soc/intel/xeon_sp: Enable PMC support ......................................................................
Patch Set 3:
(4 comments)
Please also test this on YV3.
https://review.coreboot.org/c/coreboot/+/42289/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42289/3//COMMIT_MSG@19 PS3, Line 19: select CPU_INTEL_COMMON_SMM These Kconfigs are fundamental to a slew of features. Let's add them to soc/intel/xeon_sp/Kconfig.
https://review.coreboot.org/c/coreboot/+/42289/3/src/soc/intel/xeon_sp/inclu... File src/soc/intel/xeon_sp/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/42289/3/src/soc/intel/xeon_sp/inclu... PS3, Line 13: #define PM1_STS 0x00 For the xeon_sp command header file changes, please make sure they are same for SKX-SP and CPX-SP.
https://review.coreboot.org/c/coreboot/+/42289/3/src/soc/intel/xeon_sp/pmc.c File src/soc/intel/xeon_sp/pmc.c:
https://review.coreboot.org/c/coreboot/+/42289/3/src/soc/intel/xeon_sp/pmc.c... PS3, Line 65: rtc_init(); rtc_init() is already called in romstage.c
https://review.coreboot.org/c/coreboot/+/42289/3/src/soc/intel/xeon_sp/pmuti... File src/soc/intel/xeon_sp/pmutil.c:
https://review.coreboot.org/c/coreboot/+/42289/3/src/soc/intel/xeon_sp/pmuti... PS3, Line 81: reg32 &= ~0xfff; We can use ALIGN_UP() here.