[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Update SA resource length to support 64 bit

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40336 )

Change subject: soc/intel/common/block: Update SA resource length to support 64 bit
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soc/intel/common/block: Update SA resource length to support 64 bit

This patch provides an option for accommodating 64 bit width resource
request with CONFIG_PCI_SEGMENT_GROUPS = 16 refer as PCIEX BAR length 4096MB
(Bus 0-4095).

Change-Id: I9a8448af7e9f26c8e0176e58e4fe253a6e77b69a
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40336
Reviewed-by: Wonkyu Kim 
Reviewed-by: Aaron Durbin 
Reviewed-by: Lean Sheng Tan 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/common/block/include/intelblocks/systemagent.h
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve
  Lean Sheng Tan: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
index 11ea76a..30c892b 100644
--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -31,13 +31,13 @@
  *   INDEX = Either PCI configuration space registers or MMIO offsets
  *   mapped from REG.
  *   BASE = 64 bit Address.
- *   SIZE = base length
+ *   SIZE = 64 bit base length
  *   DESCRIPTION = Name of the register/offset.
  */
 struct sa_mmio_descriptor {
    unsigned int index;
    uint64_t base;
-	size_t size;
+	uint64_t size;
    const char *description;
 };