Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33759 )
Change subject: soc/amd/picasso: Create a hybrid romstage to begin in DRAM
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Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33759/5/src/soc/amd/picasso/reset_v...
File src/soc/amd/picasso/reset_vector.S:
https://review.coreboot.org/c/coreboot/+/33759/5/src/soc/amd/picasso/reset_v...
PS5, Line 145: and $0xfffffff0, %esp
I was looking at cpu/intel/car/non-evict/cache_as_ram.S as reference.
I remembered it wrong from 2 years ago. Had gotten to the bottom of it and found documentation here https://review.coreboot.org/c/coreboot/+/20537
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