[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

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Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
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Patch Set 49:

(1 comment)

File src/soc/intel/snowridge/acpi.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/886c904c_e64e4b7c?usp... :
PS28, Line 352: 	current = acpi_create_atsr(current, cpu_domain_sa);
> atsr can be probed, can you move into the while loop?

ATSR table is determined by two parts, one is the system agent including it should have TLB enabled, the other is the root port should have the ATS extended capability structure. I searched for the `PCIE_EXT_CAP_ID_ATS` using `pciexp_find_extended_cap()` but it reports there is not such capability, but EDS says the CPU PCIe root port supports ATS, so I hard-coded it.