[coreboot-gerrit] [XS] Change in coreboot[master]: mb/intel/dcp847ske: Add Haswell-style SPD info

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76986?usp=email )

Change subject: mb/intel/dcp847ske: Add Haswell-style SPD info
......................................................................

mb/intel/dcp847ske: Add Haswell-style SPD info

Change-Id: Ied322ab68443734dffaaaafc8fe4e7747aec42c8
Signed-off-by: Keith Hui 
---
M src/mainboard/intel/dcp847ske/romstage.c
1 file changed, 7 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/76986/1

diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index e7b936a..22af5ad 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -5,9 +5,8 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #if CONFIG(USE_NATIVE_RAMINIT)
 #include <northbridge/intel/sandybridge/raminit_native.h>
-#else
-#include <northbridge/intel/sandybridge/raminit.h>
 #endif
+#include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>

#if !CONFIG(USE_NATIVE_RAMINIT)
@@ -42,3 +41,9 @@
    *pei_data = pei_data_template;
 }
 #endif
+
+void mb_get_spd_map(struct spd_info *spdi)
+{
+	spdi->addresses[0] = 0x50;
+	spdi->addresses[2] = 0x51;
+}