Attention is currently required from: Patrick Rudolph. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52776 )
Change subject: soc/intel/cannonlake: Rename `SOC_INTEL_COMETLAKE` ......................................................................
soc/intel/cannonlake: Rename `SOC_INTEL_COMETLAKE`
Rename `SOC_INTEL_COMETLAKE` to `SOC_INTEL_COMETLAKE_COMMON` making clear that it is meant for common Comet Lake configurations.
Change-Id: I993f96f032c3b76a464474c83fee4442968be152 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/me.h M src/soc/intel/cannonlake/include/soc/serialio.h M src/soc/intel/cannonlake/romstage/fsp_params.c 7 files changed, 22 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/52776/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 65277f2..1d0fe47 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -19,7 +19,7 @@ help Intel Whiskeylake support
-config SOC_INTEL_COMETLAKE +config SOC_INTEL_COMETLAKE_COMMON bool select SOC_INTEL_CANNONLAKE_BASE select FSP_USES_CB_STACK @@ -30,19 +30,19 @@
config SOC_INTEL_COMETLAKE_1 bool - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_COMMON
config SOC_INTEL_COMETLAKE_2 bool - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_COMMON
config SOC_INTEL_COMETLAKE_S bool - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_COMMON
config SOC_INTEL_COMETLAKE_V bool - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_COMMON
config SOC_INTEL_CANNONLAKE_PCH_H bool diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 7c33835..7530883 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -105,7 +105,7 @@ else ifeq ($(CONFIG_SOC_INTEL_WHISKEYLAKE),y) cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0b cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0c -else ifeq ($(CONFIG_SOC_INTEL_COMETLAKE),y) +else ifeq ($(CONFIG_SOC_INTEL_COMETLAKE_COMMON),y) ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y) cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a5-02 else diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3c8a68b..8bd98b5 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -394,7 +394,7 @@ uint8_t LanWakeFromDeepSx; uint8_t WolEnableOverride;
-#if !CONFIG(SOC_INTEL_COMETLAKE) +#if !CONFIG(SOC_INTEL_COMETLAKE_COMMON) uint32_t VrPowerDeliveryDesign; #endif
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index d7772f1..9d4b779 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -60,7 +60,7 @@
static void parse_devicetree(const config_t *config, FSP_S_CONFIG *params) { -#if CONFIG(SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE_COMMON) uint32_t dev_offset = 0; uint32_t i = 0;
@@ -163,7 +163,7 @@ sizeof(params->SataPortsDevSlp)); memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, sizeof(params->SataPortsHotPlug)); -#if CONFIG(SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE_COMMON) memcpy(params->SataPortsDevSlpResetConfig, config->SataPortsDevSlpResetConfig, sizeof(params->SataPortsDevSlpResetConfig)); @@ -276,7 +276,7 @@ params->Usb3HsioTxDownscaleAmp[i] = config->usb3_ports[i].tx_downscale_amp; } -#if CONFIG(SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE_COMMON) if (config->usb3_ports[i].gen2_tx_rate0_uniq_tran_enable) { params->Usb3HsioTxRate0UniqTranEnable[i] = 1; params->Usb3HsioTxRate0UniqTran[i] = @@ -319,13 +319,13 @@
/* Set Debug serial port */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; -#if !CONFIG(SOC_INTEL_COMETLAKE) +#if !CONFIG(SOC_INTEL_COMETLAKE_COMMON) params->SerialIoEnableDebugUartAfterPost = CONFIG(INTEL_LPSS_UART_FOR_CONSOLE); #endif
/* Enable CNVi Wifi if enabled in device tree */ dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI); -#if CONFIG(SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE_COMMON) if (dev) params->CnviMode = dev->enabled; else @@ -388,7 +388,7 @@ params->ScsSdCardEnabled = dev->enabled; params->SdCardPowerEnableActiveHigh = CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); -#if CONFIG(SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE_COMMON) params->ScsSdCardWpPinEnabled = config->ScsSdCardWpPinEnabled; #endif } @@ -437,7 +437,7 @@ if (config->PchPmSlpAMinAssert) params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
-#if CONFIG(SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE_COMMON) if (config->PchPmPwrCycDur) params->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert, config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, @@ -459,7 +459,7 @@ * The GSPI driver assumes that CS0 is the used chip-select line, * therefore only CS0 is configured below. */ -#if CONFIG(SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE_COMMON) configure_gspi_cs(0, config, ¶ms->SerialIoSpi0CsPolarity[0], ¶ms->SerialIoSpi0CsEnable[0], ¶ms->SerialIoSpiDefaultCsOutput[0]); @@ -481,7 +481,7 @@ tconfig->PchLockDownBiosInterface = 0; params->PchLockDownBiosLock = 0; params->PchLockDownRtcMemoryLock = 0; -#if CONFIG(SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE_COMMON) /* * Skip SPI Flash Lockdown from inside FSP. * Making this config "0" means FSP won't set the FLOCKDN bit @@ -496,7 +496,7 @@ tconfig->PchLockDownBiosInterface = 1; params->PchLockDownBiosLock = 1; params->PchLockDownRtcMemoryLock = 1; -#if CONFIG(SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE_COMMON) /* * Enable SPI Flash Lockdown from inside FSP. * Making this config "1" means FSP will set the FLOCKDN bit @@ -506,7 +506,7 @@ #endif }
-#if !CONFIG(SOC_INTEL_COMETLAKE) +#if !CONFIG(SOC_INTEL_COMETLAKE_COMMON) params->VrPowerDeliveryDesign = config->VrPowerDeliveryDesign; #endif
diff --git a/src/soc/intel/cannonlake/include/soc/me.h b/src/soc/intel/cannonlake/include/soc/me.h index 705bb9f..71aa8ac 100644 --- a/src/soc/intel/cannonlake/include/soc/me.h +++ b/src/soc/intel/cannonlake/include/soc/me.h @@ -18,7 +18,7 @@ u32 operation_mode: 4; u32 reset_count: 4; u32 boot_options_present: 1; -#if CONFIG(SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE_COMMON) u32 invoke_enhance_dbg_mode:1; #else u32 reserved0: 1; diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h index a5a3c16..cd08467 100644 --- a/src/soc/intel/cannonlake/include/soc/serialio.h +++ b/src/soc/intel/cannonlake/include/soc/serialio.h @@ -3,7 +3,7 @@ #ifndef _SERIALIO_H_ #define _SERIALIO_H_
-#if CONFIG(SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE_COMMON) typedef enum { PchSerialIoNotInitialized, PchSerialIoDisabled, diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5eddf85..c9f607e 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -56,7 +56,7 @@ m_cfg->PcieRpEnableMask = mask; m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; -#if CONFIG(SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE_COMMON) m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; #else m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; @@ -127,7 +127,7 @@ config->sata_port[i].TxGen3DeEmph; } } -#if !CONFIG(SOC_INTEL_COMETLAKE) +#if !CONFIG(SOC_INTEL_COMETLAKE_COMMON) if (config->DisableHeciRetry) tconfig->DisableHeciRetry = config->DisableHeciRetry; #endif