[coreboot-gerrit] Change in coreboot[master]: mb/razer/blade_stealth_kbl: 1/3 Decode raw register values

[Maxim Polyakov (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43857

to look at the new patch set (#9).

Change subject: mb/razer/blade_stealth_kbl: 1/3 Decode raw register values
......................................................................

mb/razer/blade_stealth_kbl: 1/3 Decode raw register values

Use the intelp2m utility [1,2] with -adv options to convert the pad
configuration format with the raw values of the DW0 and DW1 registers
to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(),
PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc...

./intelp2m -fld cb -t 1 -file ../../src/mainboard/razer/
blade_stealth_kbl/gpio.h

This is part of the patch set
"mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":

CB:43857 - 1/3 Decode raw register values
CB:43858 - 2/3 Exclude fields for PAD_CFG
CB:43411 - 3/3 Convert field macros to PAD_CFG

Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.

[1] https://github.com/maxpoliak/pch-pads-parser
[2] https://review.coreboot.org/c/coreboot/+/35643

Change-Id: I7c4a29f87b56c5ec7e4b74274ae677c4c08c2e8c
Signed-off-by: Maxim Polyakov 
---
M src/mainboard/razer/blade_stealth_kbl/gpio.h
1 file changed, 152 insertions(+), 152 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/43857/9