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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#15).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: 1. Default select INTEL_CAR_NEM_ENHANCED to use the existing algorithm 2. Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS a. Update eNEM init flow: - Set Non-Eviction Mask #2 MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (1 << data ways) - 1 - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1 b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/15