[coreboot-gerrit] Change in coreboot[master]: soc/intel/tgl/pcie_rp: correct root port map

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Felix Singer, Subrata Banik, Michael Niewöhner, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60943 )

Change subject: soc/intel/tgl/pcie_rp: correct root port map
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Patch Set 1:

(1 comment)

File src/soc/intel/tigerlake/pcie_rp.c:

https://review.coreboot.org/c/coreboot/+/60943/comment/01e0d2e1_6b89861f 
PS1, Line 21: static bool is_part_of_group(const struct device *dev,
            : 			     const struct pcie_rp_group *groups)
            : {
            : 	if (dev->path.type != DEVICE_PATH_PCI)
            : 		return false;
            : 
            : 	const unsigned int slot_to_find = PCI_SLOT(dev->path.pci.devfn);
            : 	const unsigned int fn_to_find = PCI_FUNC(dev->path.pci.devfn);
            : 	const struct pcie_rp_group *group;
            : 	unsigned int i;
            : 	unsigned int fn;
            : 
            : 	for (group = groups; group->count; ++group) {
            : 		for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) {
            : 			if (slot_to_find == group->slot && fn_to_find == fn)
            : 				return true;
            : 		}
            : 	}
            : 
            : 	return false;
            : }
            :
> This seems pretty generic and could be common code. The inner loop […]

It could be. The only consumer of it for now is the PMC IPC driver, which IIUC is only applicable for TGL onwards. I believe prior to TGL the RTD3 sequence for PCIe RPs was quite different and did not involve sending any PMC IPC messages.