Attention is currently required from: Anil Kumar K, Krishna P Bhat D, Subrata Banik.
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74874?usp=email )
Change subject: soc/intel/cse: Check PSR bit before issuing PSR backup command ......................................................................
Patch Set 8:
(4 comments)
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/74874/comment/921adc58_5a1011a3 : PS6, Line 1106:
the command needs to be run after CSE is in RW .. so called it after we switch to RW. […]
Acknowledged
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/74874/comment/81312d16_caadc356 : PS7, Line 1078: first check if PSR is supported by the SKU
nit: […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/74874/comment/7e722571_ac029d9f : PS7, Line 1086: /* PSR is not supported in this SKU */
you don't need this comment
Acknowledged
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/74874/comment/33b4bf1f_4a92897d : PS7, Line 43: #define ME_FW_FEATURE_PSR BIT(5)
align with line 42 (need two space may be ?)
Acknowledged