[coreboot-gerrit] Change in ...coreboot[master]: mb/intel/icelake_rvp/../icl_y: Enable SaGv

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31119

Change subject: mb/intel/icelake_rvp/../icl_y: Enable SaGv
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mb/intel/icelake_rvp/../icl_y: Enable SaGv

This patch enables SaGv on Intel ICL-Y RVP board.

TEST=Able to build and boot to Chrome OS.

Change-Id: Ic3ed94d47ddc7fd70bf3de1db15fe574029df856
Signed-off-by: Subrata Banik 
---
M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/31119/1

diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
index 0972c29..4f41308 100644
--- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
@@ -13,7 +13,7 @@
    register "gpe0_dw2" = "GPP_E"

# FSP configuration
-	register "SaGv" = "SaGv_Disabled"
+	register "SaGv" = "SaGv_Enabled"
    register "SmbusEnable" = "1"
    register "ScsEmmcHs400Enabled" = "1"
    register "SdCardPowerEnableActiveHigh" = "1"