[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Drop unreferenced devicetree settings

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48566 )

Change subject: soc/intel/alderlake: Drop unreferenced devicetree settings
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soc/intel/alderlake: Drop unreferenced devicetree settings

No mainboard uses these settings, nor does SoC code. Drop them.

Change-Id: Ib4cf88a482f840edf16e2ac42e6ab61eccfba0aa
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48566
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Michael Niewöhner 
---
M src/soc/intel/alderlake/chip.h
1 file changed, 0 insertions(+), 8 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, but someone else must approve
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 428fd4d..38d9671 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -146,12 +146,6 @@
    /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
    uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];

-	/* Integrated Sensor */
-	uint8_t PchIshEnable;
-
-	/* Heci related */
-	uint8_t Heci3Enabled;
-
    /* Gfx related */
    enum {
    	IGD_SM_0MB = 0x00,
@@ -178,8 +172,6 @@
    uint8_t InternalGfx;
    uint8_t SkipExtGfxScan;

-	uint32_t GraphicsConfigPtr;
-
    /* HeciEnabled decides the state of Heci1 at end of boot
     * Setting to 0 (default) disables Heci1 and hides the device from OS */
    uint8_t HeciEnabled;