[coreboot-gerrit] Change in coreboot[master]: sb/intel/lynxpoint/pcie: Fix clock gating routine

[Michael Niewöhner (Code Review)]

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45713 )

Change subject: sb/intel/lynxpoint/pcie: Fix clock gating routine
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sb/intel/lynxpoint/pcie: Fix clock gating routine

The use of `1 < 5` as a bit mask was obviously a typo. Correct it as
`1 << 5` to match what Intel doc #493816 (Lynx Point PCH BWG) states.

Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45713
Reviewed-by: Michael Niewöhner 
Reviewed-by: Nico Huber 
Reviewed-by: Stefan Reinauer 
Tested-by: build bot (Jenkins) 
---
M src/southbridge/intel/lynxpoint/pcie.c
1 file changed, 1 insertion(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Stefan Reinauer: Looks good to me, approved
  Nico Huber: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 112c9d3..4a245b1 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -283,8 +283,7 @@
    	/* Update PECR1 register. */
    	pci_or_config8(dev, 0xe8, 1);

-		/* FIXME: Are we supposed to update this register with a constant boolean? */
-		pci_update_config8(dev, 0x324, ~(1 << 5), (1 < 5));
+		pci_or_config8(dev, 0x324, 1 << 5);

/* Per-Port CLKREQ# handling. */
    	if (is_lp && gpio_is_native(18 + rp - 1))