Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31124 )
Change subject: mb/google/sarien/variants/arcada: Adjust TP/TS/H1 I2C CLK to meet spec ......................................................................
mb/google/sarien/variants/arcada: Adjust TP/TS/H1 I2C CLK to meet spec
After adjustment on Arcada EVT TouchScreen: 390 KHz TouchPad: 389 KHz H1: 389 KHz
BUG=b:120584026, b:120584561 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope
Signed-off-by: Casper Chang casper_chang@wistron.corp-partner.google.com Change-Id: Ia6eb332e7a664b211a5025ad07e0d01bf7f8d5bb Reviewed-on: https://review.coreboot.org/c/31124 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Lijian Zhao lijian.zhao@intel.com --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 6 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Lijian Zhao: Looks good to me, approved Casper Chang: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 2b0408e..f9d4582 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -77,17 +77,19 @@ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 52, + .fall_time_ns = 110, }, .i2c[1] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 176, - .fall_time_ns = 15, + .rise_time_ns = 52, + .fall_time_ns = 110, }, .i2c[4] = { .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 452, - .fall_time_ns = 110, + .rise_time_ns = 36, + .fall_time_ns = 99, }, }"