Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40946 )
Change subject: nb/intel/sandybridge/raminit: Add ECC debug code ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40946/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40946/1//COMMIT_MSG@12 PS1, Line 12: * ECC scrubbing must happen after dram_dimm_set_mapping()
No, the function enables the ECC logic to operate in normal mode. […]
I was asking because it's not covered by the commit summary.
https://review.coreboot.org/c/coreboot/+/40946/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit.c:
https://review.coreboot.org/c/coreboot/+/40946/1/src/northbridge/intel/sandy... PS1, Line 385: 4096
I haven't verified, but the "rank interleave" and "enhanced interleaved" that are always enabled sho […]
I'm not sure either. But with a 4096 increment, the 12 least-significant bits of all tested addresses are 0. You can take away 6 for the cache lines (those will most likely want to stick together). But that leaves 6 bits that potentially select the channel/rank and are constant 0.
There was a paper where the exact mapping for IVB was reversed, IIRC, can't find it right now :-/ there was some higher bit that got xor'd IIRC, but most channel/rank select bits were in the lower range. And I might mix things up with the cache mapping ;)