Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49136 )
Change subject: mb/intel/adlrvp: Fix wrong comments and typo
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Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49136/2/src/mainboard/intel/adlrvp/...
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49136/2/src/mainboard/intel/adlrvp/...
PS2, Line 74: Enable CPU PCIE PEG Slot 1 and 2
Exactly. I don't really understand this configuration for CLKSRC3 and CLKSRC4.
There are 3 CPU PCIE port, below is CLKREQ->CLKSRC for those ports
1. PEG 0:6:0 => 0x40
2. PEG 0:1:0 => 0x41
3. PEG 0.6.2 => 0x42
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