HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16325
-gerrit
commit 1550f7cacdd23318a6f61ec2c01377ae275344e7 Author: Elyes HAOUAS ehaouas@noos.fr Date: Thu Aug 25 21:11:45 2016 +0200
src/soc: Remove unnecessary whitespace before "\n" and "\t"
Change-Id: I89bc8b26f2dba4770aea14b8bbc7e657355e8c59 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/soc/broadcom/cygnus/ddr_init.c | 4 ++-- src/soc/intel/apollolake/gpio.c | 2 +- src/soc/intel/fsp_baytrail/southcluster.c | 2 +- src/soc/intel/sch/raminit.c | 2 +- src/soc/mediatek/mt8173/dramc_pi_calibration_api.c | 2 +- src/soc/mediatek/mt8173/pmic_wrap.c | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index abf034b..7fa2a56 100644 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -1349,7 +1349,7 @@ void ddr_init2(void)
if(pwrctli0==3) { - printk(BIOS_INFO, "\n PRE_SRX call \n"); + printk(BIOS_INFO, "\n PRE_SRX call\n"); PRE_SRX(); } #else @@ -1613,7 +1613,7 @@ void ddr_init2(void) reg32_write((unsigned int *)DDR_DENALI_CTL_56, 0x0a050505);
__udelay(200); - printk(BIOS_INFO, "\nDDR self refresh exit \n"); + printk(BIOS_INFO, "\nDDR self refresh exit\n");
// Assert DFI request from PHY to mask any interaction with MEMC reg32_write((unsigned int *)DDR_PHY_CONTROL_REGS_DFI_CNTRL, 0xe0); diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index a2ac091..1073e16 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -281,7 +281,7 @@ static void print_gpi_status(const struct gpi_status *sts)
abs_bit = bit_set; abs_bit += group * GPIO_MAX_NUM_PER_GROUP; - printk(BIOS_DEBUG, "%s %d \n",comm->grp_name, + printk(BIOS_DEBUG, "%s %d\n",comm->grp_name, abs_bit); } } diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index f493d2b..a3f4e7f 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -272,7 +272,7 @@ static void sc_pirq_init(device_t dev)
/* Set up the PIRQ PIC routing based on static config. */ printk(BIOS_SPEW, "Start writing IRQ assignments\n" - "PIRQ\tA \tB \tC \tD \tE \tF \tG \tH\n" + "PIRQ\tA\tB\tC\tD\tE\tF\tG\tH\n" "IRQ "); for (i = 0; i < NUM_PIRQS; i++) { write8(pr_base + i, ir->pic[i]); diff --git a/src/soc/intel/sch/raminit.c b/src/soc/intel/sch/raminit.c index d5ec4ef..1131510 100644 --- a/src/soc/intel/sch/raminit.c +++ b/src/soc/intel/sch/raminit.c @@ -212,7 +212,7 @@ static void do_jedec_init(struct sys_info *sysinfo) if (rank == 0) program_dll_config(sysinfo);
- printk(BIOS_DEBUG, "Setting up RAM \n"); + printk(BIOS_DEBUG, "Setting up RAM\n");
/* * Wait 200us diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index fa69f2e..0c68ad9 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -769,7 +769,7 @@ void tx_delay_for_wrleveling(u32 channel, index = i / DQS_BIT_NUMBER;
if (i % DQS_BIT_NUMBER == 0) - dramc_dbg_msg("DQS%d: %d \n", index, + dramc_dbg_msg("DQS%d: %d\n", index, wrlevel_dqs_dly[channel][index]);
if (max_dqsdly_byte[index] <= wrlevel_dqs_dly[channel][index]) { diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c index 58c9628..f4f2e37 100644 --- a/src/soc/mediatek/mt8173/pmic_wrap.c +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -127,7 +127,7 @@ s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check) /* Prevent someone to used pwrap before pwrap init */ if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) & RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { - pwrap_err("initialization isn't finished \n"); + pwrap_err("initialization isn't finished\n"); return E_PWR_NOT_INIT_DONE; } }