[coreboot-gerrit] Change in ...coreboot[master]: src/cpu/intel: Add model_f6x

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25565 )

Change subject: src/cpu/intel: Add model_f6x
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Patch Set 30:

(1 comment)

https://review.coreboot.org/#/c/25565/26/src/cpu/intel/model_f6x/model_f6x_i... 
File src/cpu/intel/model_f6x/model_f6x_init.c:

https://review.coreboot.org/#/c/25565/26/src/cpu/intel/model_f6x/model_f6x_i... 
PS26, Line 33: 	wrmsr(MSR_EBC_FREQUENCY_ID, msr_2c);
> Which datasheet did you get this from? The IA32 manual I was looking at described these MSR bits 31- […]

I'm using IA32 manual
indeed 0x2c is read-only, it was just for test to understand why the value change for CPU1 after 'setup_lapic()