[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Provide the option to enable DDR 2x refresh rate

[Gaggery Tsai (Code Review)]

Attention is currently required from: Marx Wang, Angel Pons.
Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48510 )

Change subject: soc/intel/apollolake: Provide the option to enable DDR 2x refresh rate
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Patch Set 13:

(1 comment)

Patchset:

PS13: 
This should work and I don't mind if you pass the sku pointer to meminit_lpddr4.

diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h
index 83cf809453..1ae91fbe3a 100644
--- a/src/soc/intel/apollolake/include/soc/meminit.h
+++ b/src/soc/intel/apollolake/include/soc/meminit.h
@@ -84,7 +84,7 @@ struct lpddr4_swizzle_cfg {
  * Initialize default LPDDR4 settings with provided speed. No logical channels
  * are enabled. Subsequent calls to logical channel enabling are required.
  */
-void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed);
+void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed, int rh_mitigation);

/*
  * Enable logical channel providing the full lpddr4_swizzle_config to
@@ -104,6 +104,7 @@ struct lpddr4_sku {
        int ch1_dual_rank;
        const char *part_num;
        bool disable_periodic_retraining;
+       bool row_hammer_mitigation;
 };

struct lpddr4_cfg {
diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 86015715bc..115ed6845e 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -55,7 +55,7 @@ size_t iohole_in_mib(void)
        return 2 * (GiB / MiB);
 }

-static void set_lpddr4_defaults(FSP_M_CONFIG *cfg)
+static void set_lpddr4_defaults(FSP_M_CONFIG *cfg, int rh_mitigation)
 {
        uint8_t odt_config;

@@ -68,7 +68,7 @@ static void set_lpddr4_defaults(FSP_M_CONFIG *cfg)
        cfg->SliceHashMask = 0x9;
        cfg->InterleavedMode = 2;
        cfg->ChannelsSlicesEnable = 0;
-       cfg->MinRefRate2xEnable = 0;
+       cfg->MinRefRate2xEnable = rh_mitigation;
        cfg->DualRankSupportEnable = 1;
        /* Don't enforce a memory size limit. */
        cfg->MemorySizeLimit = 0;
@@ -188,14 +188,14 @@ static int fsp_memory_profile(int speed)
        return -1;
 }

-void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed)
+void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed, int rh_mitigation)
 {
        speed = validate_speed(speed);

printk(BIOS_INFO, "LP4DDR speed is %dMHz\n", speed);
        cfg->Profile = fsp_memory_profile(speed);

-       set_lpddr4_defaults(cfg);
+       set_lpddr4_defaults(cfg, rh_mitigation);
 }

static void enable_logical_chan0(FSP_M_CONFIG *cfg,
@@ -327,7 +327,7 @@ void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg,

sku = &lpcfg->skus[sku_id];

-       meminit_lpddr4(cfg, sku->speed);
+       meminit_lpddr4(cfg, sku->speed, sku->row_hammer_mitigation);

if (sku->ch0_rank_density) {
                printk(BIOS_INFO, "LPDDR4 Ch0 density = %d\n",