Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10295
-gerrit
commit 0e411483ebd93cf868eac2c4c9bc1ea6e94d84dc Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sun May 24 09:06:03 2015 +0300
AGESA: Move S3 related SPI writes again
This is more agesawrapper-related code than CPU.
Change-Id: I3058ef965a83aed1972e02f0f566f81d5dbd7adf Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/cpu/amd/agesa/Makefile.inc | 1 - src/cpu/amd/agesa/s3_resume.c | 35 +------------- src/cpu/amd/agesa/s3_resume.h | 3 +- src/cpu/amd/agesa/spi.c | 49 -------------------- src/northbridge/amd/agesa/Makefile.inc | 3 ++ src/northbridge/amd/agesa/oem_s3.c | 83 ++++++++++++++++++++++++++++++++++ 6 files changed, 89 insertions(+), 85 deletions(-)
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index df93f3d..de4aafa 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -26,7 +26,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
romstage-y += s3_resume.c ramstage-y += s3_resume.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c
cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 15a9ee4..2ba6846 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -34,40 +34,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include "s3_resume.h"
-/* The size needs to be 4k aligned, which is the sector size of most flashes. */ -#define S3_DATA_VOLATILE_SIZE 0x6000 -#define S3_DATA_MTRR_SIZE 0x1000 -#define S3_DATA_NONVOLATILE_SIZE 0x1000 - -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ - (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE -#error "Please increase the value of S3_DATA_SIZE" -#endif - -static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) -{ - /* FIXME: Find file from CBFS. */ - u32 s3_data = CONFIG_S3_DATA_POS; - - switch (S3DataType) { - case S3DataTypeVolatile: - *pos = s3_data; - *len = S3_DATA_VOLATILE_SIZE; - break; - case S3DataTypeMTRR: - *pos = s3_data + S3_DATA_VOLATILE_SIZE; - *len = S3_DATA_MTRR_SIZE; - break; - case S3DataTypeNonVolatile: - *pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE; - *len = S3_DATA_NONVOLATILE_SIZE; - break; - default: - *pos = 0; - *len = 0; - break; - } -}
void restore_mtrr(void) { @@ -173,6 +139,7 @@ static void move_stack_high_mem(void)
#ifndef __PRE_RAM__ /* FIXME: Why store MTRR in SPI, just use CBMEM ? */ +#define S3_DATA_MTRR_SIZE 0x1000 static u8 mtrr_store[S3_DATA_MTRR_SIZE];
static void write_mtrr(u8 **p_nvram_pos, unsigned idx) diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index d7b3b89..79f6f1b 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -33,6 +33,7 @@ u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); void OemAgesaSaveMtrr (void);
-void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len); +void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len); +int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len);
#endif diff --git a/src/cpu/amd/agesa/spi.c b/src/cpu/amd/agesa/spi.c deleted file mode 100644 index 05a29d7..0000000 --- a/src/cpu/amd/agesa/spi.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <console/console.h> -#include <spi-generic.h> -#include <spi_flash.h> - -#include "s3_resume.h" - -void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) -{ - struct spi_flash *flash; - - spi_init(); - flash = spi_flash_probe(0, 0); - if (!flash) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - /* Dont make flow stop. */ - return; - } - - flash->spi->rw = SPI_WRITE_FLAG; - spi_claim_bus(flash->spi); - - flash->erase(flash, pos, size); - flash->write(flash, pos, sizeof(len), &len); - flash->write(flash, pos + sizeof(len), len, buf); - - flash->spi->rw = SPI_WRITE_FLAG; - spi_release_bus(flash->spi); - - return; -} diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 05c3c1a..284b6e2 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -30,4 +30,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb romstage-y += def_callouts.c agesawrapper.c eventlog.c ramstage-y += def_callouts.c agesawrapper.c eventlog.c
+romstage-y += oem_s3.c +ramstage-y += oem_s3.c + endif diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c new file mode 100644 index 0000000..c196be2 --- /dev/null +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <spi-generic.h> +#include <spi_flash.h> +#include <string.h> +#include <cpu/amd/agesa/s3_resume.h> + +/* The size needs to be 4k aligned, which is the sector size of most flashes. */ +#define S3_DATA_VOLATILE_SIZE 0x6000 +#define S3_DATA_MTRR_SIZE 0x1000 +#define S3_DATA_NONVOLATILE_SIZE 0x1000 + +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ + (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE +#error "Please increase the value of S3_DATA_SIZE" +#endif + +void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) +{ + /* FIXME: Find file from CBFS. */ + u32 s3_data = CONFIG_S3_DATA_POS; + + switch (S3DataType) { + case S3DataTypeVolatile: + *pos = s3_data; + *len = S3_DATA_VOLATILE_SIZE; + break; + case S3DataTypeMTRR: + *pos = s3_data + S3_DATA_VOLATILE_SIZE; + *len = S3_DATA_MTRR_SIZE; + break; + case S3DataTypeNonVolatile: + *pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE; + *len = S3_DATA_NONVOLATILE_SIZE; + break; + default: + *pos = 0; + *len = 0; + break; + } +} + +int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) +{ +#if IS_ENABLED(CONFIG_SPI_FLASH) + struct spi_flash *flash; + + spi_init(); + flash = spi_flash_probe(0, 0); + if (!flash) + return -1; + + flash->spi->rw = SPI_WRITE_FLAG; + spi_claim_bus(flash->spi); + + flash->erase(flash, pos, size); + flash->write(flash, pos, sizeof(len), &len); + flash->write(flash, pos + sizeof(len), len, buf); + + flash->spi->rw = SPI_WRITE_FLAG; + spi_release_bus(flash->spi); + return 0; +#else + return -1; +#endif +}