Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71909 )
Change subject: soc/amd/mendocino: seprate STAPM and STT for DPTC ......................................................................
soc/amd/mendocino: seprate STAPM and STT for DPTC
Seprate the STAPM and STT for the DPTC parameter. To avoid unnassary parameter been applied to DPTC, escpcialy like SPL.
BUG=b:265267957,b:265114627 BRANCH=none TEST=run Webgl aquarium with 1000 fish and no power peak observed,
Signed-off-by: Chris.Wang chris.wang@amd.corp-partner.google.com Change-Id: Ia7999753dcbb5716a3b07ef22a096b55579b80b5 --- M src/soc/amd/mendocino/Makefile.inc A src/soc/amd/mendocino/dptc.h A src/soc/amd/mendocino/dptc_acpi.c M src/soc/amd/mendocino/root_complex.c 4 files changed, 377 insertions(+), 221 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/71909/1
diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 70eb6bc..1ae79fb 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -32,6 +32,7 @@
ramstage-y += acpi.c ramstage-y += agesa_acpi.c +ramstage-y += dptc_acpi.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += fch.c diff --git a/src/soc/amd/mendocino/dptc.h b/src/soc/amd/mendocino/dptc.h new file mode 100644 index 0000000..31e0fab --- /dev/null +++ b/src/soc/amd/mendocino/dptc.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_MENDOCINO_DPTC_H +#define AMD_MENDOCINO_DPTC_H + +#include <amdblocks/alib.h> +#define DPTC_STAPM_UPDATE_PARAMS 8 +#define DPTC_STT_UPDATE_PARAMS 12 + + +struct dptc_stapm_input { + uint16_t size; + struct alib_dptc_param params[DPTC_STAPM_UPDATE_PARAMS]; +} __packed; + +struct dptc_stt_input { + uint16_t size; + struct alib_dptc_param params[DPTC_STT_UPDATE_PARAMS]; +} __packed; + +#define DPTC_STT_INPUTS(_thermctllmit, _spptTimeConst, _fast, _slow, \ + _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit, \ + _sttMinLimit, _sttM1, _sttM2, _sttCApu, _sttSkinTempLimitApu) \ + { \ + .size = sizeof(struct dptc_stt_input), \ + .params = { \ + { \ + .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \ + .value = _thermctllmit, \ + }, \ + { \ + .id = ALIB_DPTC_SLOW_PPT_TIME_CONSTANT_ID, \ + .value = _spptTimeConst, \ + }, \ + { \ + .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ + .value = _fast, \ + }, \ + { \ + .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \ + .value = _slow, \ + }, \ + { \ + .id = ALIB_DPTC_VRM_CURRENT_LIMIT_ID, \ + .value = _vrmCurrentLimit, \ + }, \ + { \ + .id = ALIB_DPTC_VRM_MAXIMUM_CURRENT_LIMIT, \ + .value = _vrmMaxCurrentLimit, \ + }, \ + { \ + .id = ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID, \ + .value = _vrmSocCurrentLimit, \ + }, \ + { \ + .id = ALIB_DPTC_STT_MIN_LIMIT_ID, \ + .value = _sttMinLimit, \ + }, \ + { \ + .id = ALIB_DPTC_STT_M1_ID, \ + .value = _sttM1, \ + }, \ + { \ + .id = ALIB_DPTC_STT_M2_ID, \ + .value = _sttM2, \ + }, \ + { \ + .id = ALIB_DPTC_STT_C_APU_ID, \ + .value = _sttCApu, \ + }, \ + { \ + .id = ALIB_DPTC_STT_SKIN_TEMPERATURE_LIMIT_APU_ID, \ + .value = _sttSkinTempLimitApu, \ + }, \ + }, \ + } + +#define DPTC_STAPM_INPUTS(_thermctllmit, _sustained, _spptTimeConst, _fast, _slow, \ + _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit) \ + { \ + .size = sizeof(struct dptc_stapm_input), \ + .params = { \ + { \ + .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \ + .value = _thermctllmit, \ + }, \ + { \ + .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \ + .value = _sustained, \ + }, \ + { \ + .id = ALIB_DPTC_SLOW_PPT_TIME_CONSTANT_ID, \ + .value = _spptTimeConst, \ + }, \ + { \ + .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ + .value = _fast, \ + }, \ + { \ + .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \ + .value = _slow, \ + }, \ + { \ + .id = ALIB_DPTC_VRM_CURRENT_LIMIT_ID, \ + .value = _vrmCurrentLimit, \ + }, \ + { \ + .id = ALIB_DPTC_VRM_MAXIMUM_CURRENT_LIMIT, \ + .value = _vrmMaxCurrentLimit, \ + }, \ + { \ + .id = ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID, \ + .value = _vrmSocCurrentLimit, \ + }, \ + }, \ + } + + +void acpigen_dptci(void); + +#endif /* AMD_MENDOCINO_DPTC_H */ diff --git a/src/soc/amd/mendocino/dptc_acpi.c b/src/soc/amd/mendocino/dptc_acpi.c new file mode 100644 index 0000000..e4193f4 --- /dev/null +++ b/src/soc/amd/mendocino/dptc_acpi.c @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> +#include <amdblocks/acpi.h> +#include <device/device.h> +#include <soc/dptc.h> +#include "chip.h" + +void acpigen_dptci(void) +{ + const struct soc_amd_mendocino_config *config = config_of_soc(); + + if (config->stt_control) { + /* Normal mode DPTC values. */ + struct dptc_stt_input default_input = DPTC_STT_INPUTS ( + config->thermctl_limit_degreeC, + config->slow_ppt_time_constant_s, + config->fast_ppt_limit_mW, + config->slow_ppt_limit_mW, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA, + config->stt_min_limit, + config->stt_m1, + config->stt_m2, + config->stt_c_apu, + config->stt_skin_temp_apu); + acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); + +#if (CONFIG(FEATURE_TABLET_MODE_DPTC)) + struct dptc_stt_input tablet_input_stt = DPTC_STT_INPUTS( + config->thermctl_limit_degreeC, + config->fast_ppt_limit_mW, + config->slow_ppt_limit_mW, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA, + config->stt_min_limit, + config->stt_m1, + config->stt_m2, + config->stt_c_apu, + config->stt_skin_temp_apu); + acpigen_write_alib_dptc_tablet((uint8_t *)&tablet_input, sizeof(tablet_input)); +#endif + +#if (CONFIG(FEATURE_DYNAMIC_DPTC)) + /* Profile B */ + struct dptc_stt_input thermal_B_input = DPTC_STT_INPUTS( + config->thermctl_limit_degreeC, + config->slow_ppt_time_constant_s_B, + config->fast_ppt_limit_mW_B, + config->slow_ppt_limit_mW_B, + config->vrm_current_limit_throttle_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA, + config->stt_min_limit_B, + config->stt_m1_B, + config->stt_m2_B, + config->stt_c_apu_B, + config->stt_skin_temp_apu_B); + acpigen_write_alib_dptc_thermal_B((uint8_t *)&thermal_B_input, + sizeof(thermal_B_input)); + + /* Profile C */ + struct dptc_stt_input thermal_C_input = DPTC_STT_INPUTS( + config->thermctl_limit_degreeC, + config->slow_ppt_time_constant_s_C, + config->fast_ppt_limit_mW_C, + config->slow_ppt_limit_mW_C, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA, + config->stt_min_limit_C, + config->stt_m1_C, + config->stt_m2_C, + config->stt_c_apu_C, + config->stt_skin_temp_apu_C); + acpigen_write_alib_dptc_thermal_C((uint8_t *)&thermal_C_input, + sizeof(thermal_C_input)); + + /* Profile D */ + struct dptc_stt_input thermal_D_input = DPTC_STT_INPUTS( + config->thermctl_limit_degreeC, + config->slow_ppt_time_constant_s_D, + config->fast_ppt_limit_mW_D, + config->slow_ppt_limit_mW_D, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA, + config->stt_min_limit_D, + config->stt_m1_D, + config->stt_m2_D, + config->stt_c_apu_D, + config->stt_skin_temp_apu_D); + acpigen_write_alib_dptc_thermal_D((uint8_t *)&thermal_D_input, + sizeof(thermal_D_input)); + + /* Profile E */ + struct dptc_stt_input thermal_E_input = DPTC_STT_INPUTS( + config->thermctl_limit_degreeC, + config->slow_ppt_time_constant_s_E, + config->fast_ppt_limit_mW_E, + config->slow_ppt_limit_mW_E, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA, + config->stt_min_limit_E, + config->stt_m1_E, + config->stt_m2_E, + config->stt_c_apu_E, + config->stt_skin_temp_apu_E); + acpigen_write_alib_dptc_thermal_E((uint8_t *)&thermal_E_input, + sizeof(thermal_E_input)); + + /* Profile F */ + struct dptc_stt_input thermal_F_input = DPTC_STT_INPUTS( + config->thermctl_limit_degreeC, + config->slow_ppt_time_constant_s_F, + config->fast_ppt_limit_mW_F, + config->slow_ppt_limit_mW_F, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA, + config->stt_min_limit_F, + config->stt_m1_F, + config->stt_m2_F, + config->stt_c_apu_F, + config->stt_skin_temp_apu_F); + acpigen_write_alib_dptc_thermal_F((uint8_t *)&thermal_F_input, + sizeof(thermal_F_input)); +#endif + } else { + struct dptc_stapm_input default_input = DPTC_STAPM_INPUTS ( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW, + config->slow_ppt_time_constant_s, + config->fast_ppt_limit_mW, + config->slow_ppt_limit_mW, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); + /* Low/No Battery */ + struct dptc_stapm_input no_battery_input = DPTC_STAPM_INPUTS( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW, + config->slow_ppt_time_constant_s, + config->fast_ppt_limit_mW, + config->slow_ppt_limit_mW, + config->vrm_current_limit_throttle_mA, + config->vrm_maximum_current_limit_throttle_mA, + config->vrm_soc_current_limit_throttle_mA); + acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input, + sizeof(no_battery_input)); + +#if (CONFIG(FEATURE_TABLET_MODE_DPTC)) + struct dptc_stapm_input tablet_input = DPTC_STAPM_INPUTS( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW_tablet, + config->slow_ppt_time_constant_s, + config->fast_ppt_limit_mW, + config->slow_ppt_limit_mW, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_tablet((uint8_t *)&tablet_input, sizeof(tablet_input)); +#endif + +#if (CONFIG(FEATURE_DYNAMIC_DPTC)) + /* Profile B */ + struct dptc_stapm_input thermal_B_input = DPTC_STAPM_INPUTS( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW_B, + config->slow_ppt_time_constant_s_B, + config->fast_ppt_limit_mW_B, + config->slow_ppt_limit_mW_B, + config->vrm_current_limit_throttle_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_B((uint8_t *)&thermal_B_input, + sizeof(thermal_B_input)); + + /* Profile C */ + struct dptc_stapm_input thermal_C_input = DPTC_STAPM_INPUTS( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW_C, + config->slow_ppt_time_constant_s_C, + config->fast_ppt_limit_mW_C, + config->slow_ppt_limit_mW_C, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_C((uint8_t *)&thermal_C_input, + sizeof(thermal_C_input)); + + /* Profile D */ + struct dptc_stapm_input thermal_D_input = DPTC_STAPM_INPUTS( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW_D, + config->slow_ppt_time_constant_s_D, + config->fast_ppt_limit_mW_D, + config->slow_ppt_limit_mW_D, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_D((uint8_t *)&thermal_D_input, + sizeof(thermal_D_input)); + + /* Profile E */ + struct dptc_stapm_input thermal_E_input = DPTC_STAPM_INPUTS( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW_E, + config->slow_ppt_time_constant_s_E, + config->fast_ppt_limit_mW_E, + config->slow_ppt_limit_mW_E, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_E((uint8_t *)&thermal_E_input, + sizeof(thermal_E_input)); + + /* Profile F */ + struct dptc_stapm_input thermal_F_input = DPTC_STAPM_INPUTS( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW_F, + config->slow_ppt_time_constant_s_F, + config->fast_ppt_limit_mW_F, + config->slow_ppt_limit_mW_F, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_F((uint8_t *)&thermal_F_input, + sizeof(thermal_F_input)); +#endif + } +} diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 5185936..acea5d0 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
/* TODO: Check if this is still correct */ - #include <acpi/acpigen.h> #include <amdblocks/acpi.h> #include <amdblocks/alib.h> @@ -14,78 +13,10 @@ #include <device/pci.h> #include <fsp/util.h> #include <soc/iomap.h> +#include <soc/dptc.h> #include <stdint.h> #include "chip.h"
-#define DPTC_TOTAL_UPDATE_PARAMS 13 - -struct dptc_input { - uint16_t size; - struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; -} __packed; - - -#define DPTC_INPUTS(_thermctllmit, _sustained, _spptTimeConst, _fast, _slow, \ - _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit, \ - _sttMinLimit, _sttM1, _sttM2, _sttCApu, _sttSkinTempLimitApu) \ - { \ - .size = sizeof(struct dptc_input), \ - .params = { \ - { \ - .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \ - .value = _thermctllmit, \ - }, \ - { \ - .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \ - .value = _sustained, \ - }, \ - { \ - .id = ALIB_DPTC_SLOW_PPT_TIME_CONSTANT_ID, \ - .value = _spptTimeConst, \ - }, \ - { \ - .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ - .value = _fast, \ - }, \ - { \ - .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \ - .value = _slow, \ - }, \ - { \ - .id = ALIB_DPTC_VRM_CURRENT_LIMIT_ID, \ - .value = _vrmCurrentLimit, \ - }, \ - { \ - .id = ALIB_DPTC_VRM_MAXIMUM_CURRENT_LIMIT, \ - .value = _vrmMaxCurrentLimit, \ - }, \ - { \ - .id = ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID, \ - .value = _vrmSocCurrentLimit, \ - }, \ - { \ - .id = ALIB_DPTC_STT_MIN_LIMIT_ID, \ - .value = _sttMinLimit, \ - }, \ - { \ - .id = ALIB_DPTC_STT_M1_ID, \ - .value = _sttM1, \ - }, \ - { \ - .id = ALIB_DPTC_STT_M2_ID, \ - .value = _sttM2, \ - }, \ - { \ - .id = ALIB_DPTC_STT_C_APU_ID, \ - .value = _sttCApu, \ - }, \ - { \ - .id = ALIB_DPTC_STT_SKIN_TEMPERATURE_LIMIT_APU_ID, \ - .value = _sttSkinTempLimitApu, \ - }, \ - }, \ - } - /* * * +--------------------------------+ @@ -215,161 +146,11 @@ register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); }
-static void acipgen_dptci(void) -{ - const struct soc_amd_mendocino_config *config = config_of_soc(); - - /* Normal mode DPTC values. */ - struct dptc_input default_input = DPTC_INPUTS( - config->thermctl_limit_degreeC, - config->sustained_power_limit_mW, - config->slow_ppt_time_constant_s, - config->fast_ppt_limit_mW, - config->slow_ppt_limit_mW, - config->vrm_current_limit_mA, - config->vrm_maximum_current_limit_mA, - config->vrm_soc_current_limit_mA, - config->stt_min_limit, - config->stt_m1, - config->stt_m2, - config->stt_c_apu, - config->stt_skin_temp_apu); - acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); - - /* Low/No Battery */ - struct dptc_input no_battery_input = DPTC_INPUTS( - config->thermctl_limit_degreeC, - config->sustained_power_limit_mW, - config->slow_ppt_time_constant_s, - config->fast_ppt_limit_mW, - config->slow_ppt_limit_mW, - config->vrm_current_limit_throttle_mA, - config->vrm_maximum_current_limit_throttle_mA, - config->vrm_soc_current_limit_throttle_mA, - config->stt_min_limit, - config->stt_m1, - config->stt_m2, - config->stt_c_apu, - config->stt_skin_temp_apu); - acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input, - sizeof(no_battery_input)); - -#if (CONFIG(FEATURE_TABLET_MODE_DPTC)) - struct dptc_input tablet_input = DPTC_INPUTS( - config->thermctl_limit_degreeC, - config->sustained_power_limit_mW_tablet, - config->slow_ppt_time_constant_s, - config->fast_ppt_limit_mW, - config->slow_ppt_limit_mW, - config->vrm_current_limit_mA, - config->vrm_maximum_current_limit_mA, - config->vrm_soc_current_limit_mA, - config->stt_min_limit, - config->stt_m1, - config->stt_m2, - config->stt_c_apu, - config->stt_skin_temp_apu); - acpigen_write_alib_dptc_tablet((uint8_t *)&tablet_input, sizeof(tablet_input)); -#endif - -#if (CONFIG(FEATURE_DYNAMIC_DPTC)) - /* Profile B */ - struct dptc_input thermal_B_input = DPTC_INPUTS( - config->thermctl_limit_degreeC, - config->sustained_power_limit_mW_B, - config->slow_ppt_time_constant_s_B, - config->fast_ppt_limit_mW_B, - config->slow_ppt_limit_mW_B, - config->vrm_current_limit_throttle_mA, - config->vrm_maximum_current_limit_mA, - config->vrm_soc_current_limit_mA, - config->stt_min_limit_B, - config->stt_m1_B, - config->stt_m2_B, - config->stt_c_apu_B, - config->stt_skin_temp_apu_B); - acpigen_write_alib_dptc_thermal_B((uint8_t *)&thermal_B_input, - sizeof(thermal_B_input)); - - /* Profile C */ - struct dptc_input thermal_C_input = DPTC_INPUTS( - config->thermctl_limit_degreeC, - config->sustained_power_limit_mW_C, - config->slow_ppt_time_constant_s_C, - config->fast_ppt_limit_mW_C, - config->slow_ppt_limit_mW_C, - config->vrm_current_limit_mA, - config->vrm_maximum_current_limit_mA, - config->vrm_soc_current_limit_mA, - config->stt_min_limit_C, - config->stt_m1_C, - config->stt_m2_C, - config->stt_c_apu_C, - config->stt_skin_temp_apu_C); - acpigen_write_alib_dptc_thermal_C((uint8_t *)&thermal_C_input, - sizeof(thermal_C_input)); - - /* Profile D */ - struct dptc_input thermal_D_input = DPTC_INPUTS( - config->thermctl_limit_degreeC, - config->sustained_power_limit_mW_D, - config->slow_ppt_time_constant_s_D, - config->fast_ppt_limit_mW_D, - config->slow_ppt_limit_mW_D, - config->vrm_current_limit_mA, - config->vrm_maximum_current_limit_mA, - config->vrm_soc_current_limit_mA, - config->stt_min_limit_D, - config->stt_m1_D, - config->stt_m2_D, - config->stt_c_apu_D, - config->stt_skin_temp_apu_D); - acpigen_write_alib_dptc_thermal_D((uint8_t *)&thermal_D_input, - sizeof(thermal_D_input)); - - /* Profile E */ - struct dptc_input thermal_E_input = DPTC_INPUTS( - config->thermctl_limit_degreeC, - config->sustained_power_limit_mW_E, - config->slow_ppt_time_constant_s_E, - config->fast_ppt_limit_mW_E, - config->slow_ppt_limit_mW_E, - config->vrm_current_limit_mA, - config->vrm_maximum_current_limit_mA, - config->vrm_soc_current_limit_mA, - config->stt_min_limit_E, - config->stt_m1_E, - config->stt_m2_E, - config->stt_c_apu_E, - config->stt_skin_temp_apu_E); - acpigen_write_alib_dptc_thermal_E((uint8_t *)&thermal_E_input, - sizeof(thermal_E_input)); - - /* Profile F */ - struct dptc_input thermal_F_input = DPTC_INPUTS( - config->thermctl_limit_degreeC, - config->sustained_power_limit_mW_F, - config->slow_ppt_time_constant_s_F, - config->fast_ppt_limit_mW_F, - config->slow_ppt_limit_mW_F, - config->vrm_current_limit_mA, - config->vrm_maximum_current_limit_mA, - config->vrm_soc_current_limit_mA, - config->stt_min_limit_F, - config->stt_m1_F, - config->stt_m2_F, - config->stt_c_apu_F, - config->stt_skin_temp_apu_F); - acpigen_write_alib_dptc_thermal_F((uint8_t *)&thermal_F_input, - sizeof(thermal_F_input)); -#endif -} - static void root_complex_fill_ssdt(const struct device *device) { acpi_fill_root_complex_tom(device); if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) - acipgen_dptci(); + acpigen_dptci(); }
static const char *gnb_acpi_name(const struct device *dev)