[coreboot-gerrit] Change in coreboot[master]: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config

[Amanda Hwang (Code Review)]

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Amanda Hwang.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/55000

to look at the new patch set (#2).

Change subject: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config
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util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config

CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config")
incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B
part has 2 channels per die and 2 physical dies. Each channel in each die
shares DQ-DQS lines with the channel in other die and uses separate CS
lines. Thus, number of ranks per channel is 2.

This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B
in LP4x global config by setting it to 2.

BUG=b:186616388

Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba
Signed-off-by: Amanda Huang 
---
M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/55000/2