Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40335 )
Change subject: soc/intel/common/block/acpi: Add provision for multiple PCI segments ......................................................................
Patch Set 5:
Patch Set 5:
Before we dive deeper into this, can please discuss the reason behind it?
Nothing specific rather ensuring Intel Common Code has support for latest SoC release with EDS been updated with new features.
What can/will it be used for?
To incorporate any devices sitting at Segment 1.
Does ICL really have multiple PCI segments?
If a platform supports more than 256 buses, then it should support multi-segment. It aligns with the below description in the EDS. TGL as you know supports 2 segments, 1 for TBT and 1 for the rest of the devices which adds up to a total of 512 buses.
What devices are on the other segments?
Now you have answer based on above question
Why do we suddenly need to give the OS access to these devices?
Ideally configuration mechanism makes use of memory mapped address space range/s to access PCI configuration space. Put simply, the memory address determines the segment group, bus, device, function and register being accessed. On x86 and x64 platforms, the address of each memory area is determined by the ACPI 'MCFG' table. Thought of updating correct information to OS via MCFG as applicable for platform.