Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/20418
Change subject: Fizz: Set PL2 and PsysPL2 MSRs ......................................................................
Fizz: Set PL2 and PsysPL2 MSRs
BUG=b:7473486, b:35775024 BRANCH=None TEST=On bootup make sure PL2 and PsysPL2 values set properly (through debug output)
Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c Signed-off-by: Shelley Chen shchen@chromium.org --- M src/mainboard/google/fizz/devicetree.cb M src/mainboard/google/fizz/mainboard.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/msr.h 5 files changed, 71 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/20418/1
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index a493de5..d0bddba 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -210,7 +210,6 @@ }"
register "speed_shift_enable" = "1" - register "tdp_pl2_override" = "7" register "tcc_offset" = "10" # TCC of 90C
# Use default SD card detect GPIO configuration diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index a925f08..4eb12d4 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <device/device.h> #include <ec/ec.h> +#include <soc/cpu.h> #include <soc/pci_devs.h> #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -24,6 +25,41 @@ static const char *oem_id = "GOOGLE"; static const char *oem_table_id = "FIZZ";
+/* + * mainboard_get_pl2 + * + * @return value Pl2 should be set to based on cpu id + * + * NOTE: This is purely based on cpu id, which only work for the + * current build because we have a different cpu id per sku. However, + * on the next build, we'll have distinct board ids per sku. We'll + * need to modify that at this point. + */ +u32 mainboard_get_pl2(void) +{ + struct cpuid_result cpuidr; + + cpuidr = cpuid(1); + printk(BIOS_DEBUG, "CPU(1): 0x%x\n", cpuidr.eax); + if (cpuidr.eax == 0x806ea) { + /* i7 needs higher pl2 */ + return 44; + } + return 29; +} + +/* + * mainboard_get_psyspl2 + * + * This is 90 Watts across all SKUs for Fizz + * + * @return value PsysPl2 should be set to + */ +u32 mainboard_get_psyspl2(void) +{ + return 90; +} + static void mainboard_init(device_t dev) { mainboard_ec_init(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index e3be738..825fd15 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -104,6 +104,19 @@ [0x11] = 128, };
+u32 __attribute__((weak)) mainboard_get_pl2(void) +{ + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; + + return conf->tdp_pl2_override; +} + +u32 __attribute__((weak)) mainboard_get_psyspl2(void) +{ + return 0; +} + /* * Configure processor power limits if possible * This must be done AFTER set of BIOS_RESET_CPL @@ -115,8 +128,8 @@ unsigned int power_unit; unsigned int tdp, min_power, max_power, max_time, tdp_pl2; u8 power_limit_1_val; - device_t dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; + u32 pl2_val; + u32 psyspl2_val;
if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) power_limit_1_time = 28; @@ -159,10 +172,12 @@ limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
- /* Set short term power limit to 1.25 * TDP */ + /* Set short term power limit to 1.25 TDP if no config given */ limit.hi = 0; - tdp_pl2 = (conf->tdp_pl2_override == 0) ? - (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit); + pl2_val = mainboard_get_pl2(); + tdp_pl2 = (pl2_val == 0) ? + (tdp * 125) / 100 : (pl2_val * power_unit); + printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", pl2_val); limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK; limit.hi |= PKG_POWER_LIMIT_CLAMP; limit.hi |= PKG_POWER_LIMIT_EN; @@ -174,6 +189,18 @@ MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN)); MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi;
+ /* Set PsysPl2 */ + limit.lo = 0; + limit.hi = 0; + psyspl2_val = mainboard_get_psyspl2(); + if (psyspl2_val) { + printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", psyspl2_val); + limit.hi |= (psyspl2_val) & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + + wrmsr(MSR_PLATFORM_POWER_LIMIT, limit); + } + /* Set DDR RAPL power limit by copying from MMIO to MSR */ msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 059367a..47d3e63 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -50,6 +50,8 @@ (IRTL_1024_NS >> 10))
/* Configure power limits for turbo mode */ +u32 mainboard_get_pl2(void); +u32 mainboard_get_psyspl2(void); void set_power_limits(u8 power_limit_1_time);
/* CPU identification */ diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index bb4b8e7..ef4027a 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -41,5 +41,6 @@ #define MSR_VR_MISC_CONFIG2 0x636 #define MSR_PP0_POWER_LIMIT 0x638 #define MSR_PP1_POWER_LIMIT 0x640 +#define MSR_PLATFORM_POWER_LIMIT 0x65c
#endif