Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39847 )
Change subject: soc/intel/tigerlake: Support to initialize Memory ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39847/5/src/soc/intel/tigerlake/mem... File src/soc/intel/tigerlake/meminit_tgl.c:
https://review.coreboot.org/c/coreboot/+/39847/5/src/soc/intel/tigerlake/mem... PS5, Line 179: meminit_ddr4x_sodimm
Okay
Here you go: https://review.coreboot.org/c/coreboot/+/39865
I have also added some basic header file changes to support DDR4 that you can build up on: https://review.coreboot.org/c/coreboot/+/39866
This is what I think you will have to do: a) Add ddr4_cfg structure b) Implement meminit_ddr4(...) In this function, you can set all params specific to DDR4 and then for SPD you will have to handle in following ways: i. As per EDS, if mixed configuration is used, ch0 should always be MD. Thus, if memory topology is mixed or MD, then you will have to use read_md_spd() to read out SPD information. Else, use read_smbus_spd()[You will have to implement this to read SPD via SMBus in coreboot]. Then, initialize channel1 by calling init_spd_upds(), init_dq_upds(), init_dqs_upds().
ii. For channel 2, if memory topology is MD, you can reuse SPD from above. Else, you will have to call read_smbus_spd() to read SPD. Then, initialize channel2 by calling init_spd_upds(), init_dq_upds(), init_dqs_upds().
For SODIMM configurations, each channel can support upto 2 DIMMs. So, you will have to ensure that you handle it appropriately and pass in right information into init_spd_upds().
https://review.coreboot.org/c/coreboot/+/39847/5/src/soc/intel/tigerlake/mem... PS5, Line 193: SpdAddressTable There is no need to set SpdAddressTable. Coreboot can read SPD data using SMBus and directly pass that information into FSP.