HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15984
-gerrit
commit b508714a0941ea3d57ffb17e261880e505fa72bf Author: Elyes HAOUAS ehaouas@noos.fr Date: Sat Jul 30 15:44:17 2016 +0200
src/include: Capitalize CPU, ROM, RAM and APIC
Change-Id: I09ab0564ec1cc837d721d9bc242111bf9d410f81 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/include/cbfs.h | 2 +- src/include/console/post_codes.h | 6 +++--- src/include/cpu/x86/cache.h | 2 +- src/include/cpu/x86/lapic.h | 2 +- src/include/cpu/x86/mp.h | 12 ++++++------ src/include/cpu/x86/msr.h | 2 +- src/include/cpu/x86/mtrr.h | 2 +- src/include/cpu/x86/smm.h | 10 +++++----- src/include/gic.h | 2 +- src/include/rmodule.h | 2 +- 10 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 2d19218..6d9dd42 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -23,7 +23,7 @@ * Perform CBFS operations on the boot device. * ***********************************************/
-/* Return mapping of option rom found in boot device. NULL on error. */ +/* Return mapping of option ROM found in boot device. NULL on error. */ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device); /* Load stage by name into memory. Returns entry address on success. NULL on * failure. */ diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 8e47905..c7722e5 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -82,14 +82,14 @@ #define POST_ENTRY_C_START 0x13
/** - * \brief Pre call to ram stage main() + * \brief Pre call to RAM stage main() * - * POSTed right before ram stage main() is called from c_start.S + * POSTed right before RAM stage main() is called from c_start.S */ #define POST_PRE_HARDWAREMAIN 0x79
/** - * \brief Entry into coreboot in ram stage main() + * \brief Entry into coreboot in RAM stage main() * * This is the first call in hardwaremain.c. If this code is POSTed, then * ramstage has successfully loaded and started executing. diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 9c1af29..a446bbe 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -52,7 +52,7 @@ static inline void invd(void)
/* The following functions require the always_inline due to AMD * function STOP_CAR_AND_CPU that disables cache as - * ram, the cache as ram stack can no longer be used. Called + * ram, the cache as RAM stack can no longer be used. Called * functions must be inlined to avoid stack usage. Also, the * compiler must keep local variables register based and not * allocated them from the stack. With gcc 4.5.0, some functions diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 16bc42d..dfcb4da 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -6,7 +6,7 @@ #include <halt.h> #include <smp/node.h>
-/* See if I need to initialize the local apic */ +/* See if I need to initialize the local APIC */ #if CONFIG_SMP || CONFIG_IOAPIC # define NEED_LAPIC 1 #else diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 9742df0..cea3139 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -59,9 +59,9 @@ struct mp_ops { void (*get_microcode_info)(const void **microcode, int *parallel); /* * Optionally provide a function which adjusts the APIC id - * map to cpu number. By default the cpu number and APIC id - * are 1:1. To change the APIC id for a given cpu return the - * new APIC id. It's called for each cpu as indicated by + * map to CPU number. By default the CPU number and APIC id + * are 1:1. To change the APIC id for a given CPU return the + * new APIC id. It's called for each CPU as indicated by * get_cpu_count(). */ int (*adjust_cpu_apic_entry)(int cpu, int cur_apic_id); @@ -78,7 +78,7 @@ struct mp_ops { void (*adjust_smm_params)(struct smm_loader_params *slp, int is_perm); /* * Optionally provide a callback prior to the APs starting SMM - * relocation or cpu driver initialization. However, note that + * relocation or CPU driver initialization. However, note that * this callback is called after SMM handlers have been loaded. */ void (*pre_mp_smm_init)(void); @@ -88,11 +88,11 @@ struct mp_ops { */ void (*per_cpu_smm_trigger)(void); /* - * This function is called while each cpu is in the SMM relocation + * This function is called while each CPU is in the SMM relocation * handler. Its primary purpose is to adjust the SMBASE for the * permanent handler. The parameters passed are the current cpu * running the relocation handler, current SMBASE of relocation handler, - * and the pre-calculated staggered cpu SMBASE address of the permanent + * and the pre-calculated staggered CPU SMBASE address of the permanent * SMM handler. */ void (*relocation_handler)(int cpu, uintptr_t curr_smbase, diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index d644edd..151c9dc 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -48,7 +48,7 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index,
/* The following functions require the always_inline due to AMD * function STOP_CAR_AND_CPU that disables cache as - * ram, the cache as ram stack can no longer be used. Called + * ram, the cache as RAM stack can no longer be used. Called * functions must be inlined to avoid stack usage. Also, the * compiler must keep local variables register based and not * allocated them from the stack. With gcc 4.5.0, some functions diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index d09c77e..f32bece 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -91,7 +91,7 @@ int get_free_var_mtrr(void); (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x))
-/* At the end of romstage, low ram 0..CACHE_TM_RAMTOP may be set +/* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set * as write-back cacheable to speed up ramstage decompression. * Note MTRR boundaries, must be power of two. */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 2b13f8c..9d7e6a1 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -491,8 +491,8 @@ u16 smm_get_pmbase(void); struct smm_runtime { u32 smbase; u32 save_state_size; - /* The apic_id_to_cpu provides a mapping from APIC id to cpu number. - * The cpu number is indicated by the index into the array by matching + /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. + * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader * initializes this array with a 1:1 mapping. If the APIC ids are not * contiguous like the 1:1 mapping it is up to the caller of the stub @@ -525,7 +525,7 @@ void *smm_get_save_state(int cpu); /* The smm_loader_params structure provides direction to the SMM loader: * - stack_top - optional external stack provided to loader. It must be at * least per_cpu_stack_size * num_concurrent_stacks in size. - * - per_cpu_stack_size - stack size per cpu for smm modules. + * - per_cpu_stack_size - stack size per CPU for smm modules. * - num_concurrent_stacks - number of concurrent cpus in handler needing stack * optional for setting up relocation handler. * - per_cpu_save_state_size - the smm save state size per cpu @@ -537,8 +537,8 @@ void *smm_get_save_state(int cpu); * the address of the module's parameters (if present). * - runtime - this field is a result only. The SMM runtime location is filled * into this field so the code doing the loading can manipulate the - * runtime's assumptions. e.g. updating the apic id to cpu map to - * handle sparse apic id space. + * runtime's assumptions. e.g. updating the APIC id to CPU map to + * handle sparse APIC id space. */ struct smm_loader_params { void *stack_top; diff --git a/src/include/gic.h b/src/include/gic.h index 1ac1eab..f7339a4 100644 --- a/src/include/gic.h +++ b/src/include/gic.h @@ -26,7 +26,7 @@ void gic_enable(void); /* Return a pointer to the base of the GIC distributor mmio region. */ void *gicd_base(void);
-/* Return a pointer to the base of the GIC cpu mmio region. */ +/* Return a pointer to the base of the GIC CPU mmio region. */ void *gicc_base(void);
#else /* CONFIG_GIC */ diff --git a/src/include/rmodule.h b/src/include/rmodule.h index c0c062c..c5de9c3 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -40,7 +40,7 @@ int rmodule_load_alignment(const struct rmodule *m); /* rmodule_calc_region() calculates the region size, offset to place an * rmodule in memory, and load address offset based off of a region allocator * with an alignment of region_alignment. This function helps place an rmodule - * in the same location in ram it will run from. The offset to place the + * in the same location in RAM it will run from. The offset to place the * rmodule into the region allocated of size region_size is returned. The * load_offset is the address to load and relocate the rmodule. * region_alignment must be a power of 2. */