Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62093 )
Change subject: nb/amd/amdfam10/bootblock.c: Fix comments style ......................................................................
nb/amd/amdfam10/bootblock.c: Fix comments style
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I66dd0f96e7435d6b75c8fe070d44c43e0816e5db --- M src/northbridge/amd/amdfam10/bootblock.c 1 file changed, 26 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/62093/1
diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c index ac28334..59ae732 100644 --- a/src/northbridge/amd/amdfam10/bootblock.c +++ b/src/northbridge/amd/amdfam10/bootblock.c @@ -30,37 +30,41 @@ dword = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x68); dword |= (1<<27) | (1<<25); /* CHtExtNodeCfgEn: coherent link extended node configuration enable, - Nodes[31:0] will be 0xff:[31:0], Nodes[63:32] will be 0xfe:[31:0] - ---- 32 nodes now only - It can be used even nodes less than 8 nodes. - We can have 8 more device on bus 0 in that case + * Nodes[31:0] will be 0xff:[31:0], Nodes[63:32] will be 0xfe:[31:0] + * ---- 32 nodes now only + * It can be used even nodes less than 8 nodes. + * We can have 8 more device on bus 0 in that case */
/* CHtExtAddrEn */ pci_write_config32(PCI_DEV(0, 0x18, 0), 0x68, dword); - // CPU on bus 0xff and 0xfe now. For now on we can use CONFIG_CBB and CONFIG_CDB. + /* CPU on bus 0xff and 0xfe now. For now on we can use CONFIG_CBB and CONFIG_CDB. */ }
static void enumerate_ht_chain(void) {
- /* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), - * if so, don't need to go through the chain + /* + * CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht + * chain), if so, don't need to go through the chain */ if (CONFIG_HT_CHAIN_UNITID_BASE == 0) return;
- /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a CPU has multiple - * non Coherent links the appropriate bus registers for the - * links needs to be programed to point at bus 0. + /* + * Assumption the HT chain that is bus 0 has the HT I/O Hub on it. On + * most boards this just happens. If a CPU has multiple non Coherent + * links the appropriate bus registers for the links needs to be + * programed to point at bus 0. */ unsigned int next_unitid, last_unitid = 0; - // let't record the device of last ht device, So we can set the - // Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE + /* + * Let's record the device of last ht device, So we can set the Unitid + * to CONFIG_HT_CHAIN_END_UNITID_BASE + */ unsigned int real_last_unitid = 0; u8 real_last_pos = 0; - int ht_dev_num = 0; // except host_bridge + int ht_dev_num = 0; /* except host_bridge */ u8 end_used = 0;
next_unitid = CONFIG_HT_CHAIN_UNITID_BASE; @@ -92,7 +96,8 @@ cap = pci_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID); if (cap == PCI_CAP_ID_HT) { u16 flags; - /* Read and write and reread flags so the link + /* + * Read and write and reread flags so the link * direction bit is valid. */ flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); @@ -153,7 +158,7 @@ pci_write_config16(devx, pos + ctrl_off, ctrl); ctrl = pci_read_config16(devx, pos + ctrl_off); if (ctrl & ((1 << 4) | (1 << 8))) { - // can not clear the error + /* Can not clear the error */ break; } } @@ -180,9 +185,11 @@ }
void bootblock_early_northbridge_init(void) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ + /* + * Nothing special needs to be done to find bus 0. + * Allow the HT devices to be found. + * Move bsp to bus 0xff when > 8 nodes. + */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); }