[coreboot-gerrit] Change in coreboot[master]: soc/mediatek: Add timestamp to measure PERST# time

[Jianjun Wang (Code Review)]

Jianjun Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62933 )

Change subject: soc/mediatek: Add timestamp to measure PERST# time
......................................................................

soc/mediatek: Add timestamp to measure PERST# time

Add timestamp support to measure the assertion time of PERST#.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024

Signed-off-by: Jianjun Wang 
Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71
---
M src/mainboard/google/cherry/bootblock.c
M src/soc/mediatek/common/pcie.c
2 files changed, 34 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/62933/1

diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c
index dd83817..f5839ab 100644
--- a/src/mainboard/google/cherry/bootblock.c
+++ b/src/mainboard/google/cherry/bootblock.c
@@ -1,12 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <bootblock_common.h>
+#include <console/console.h>
 #include <device/mmio.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <soc/i2c.h>
 #include <soc/pcie.h>
 #include <soc/spi.h>
+#include <soc/symbols.h>
+#include <timestamp.h>

#include "gpio.h"

@@ -44,9 +47,16 @@

void bootblock_mainboard_init(void)
 {
-	if (CONFIG(PCI))
+	if (CONFIG(PCI)) {
    	mtk_pcie_pre_init();

+		if (CONFIG(COLLECT_TIMESTAMPS) &&
+		    REGION_SIZE(pcie_timestamp) > 0) {
+			uint64_t timestamp = timestamp_get();
+			write64(_pcie_timestamp, timestamp);
+		}
+	}
+
    mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST);
    mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
    nor_set_gpio_pinmux();
diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c
index c46b53f..839ff56 100644
--- a/src/soc/mediatek/common/pcie.c
+++ b/src/soc/mediatek/common/pcie.c
@@ -14,7 +14,9 @@
 #include <soc/pcie.h>
 #include <soc/pcie_common.h>
 #include <soc/soc_chip.h>
+#include <soc/symbols.h>
 #include <stdlib.h>
+#include <timestamp.h>
 #include <types.h>

#define PCIE_SETTING_REG		0x80
@@ -233,6 +235,27 @@
    val &= ~PCIE_INTX_ENABLE;
    write32p(conf->base + PCIE_INT_ENABLE_REG, val);

+	if (CONFIG(COLLECT_TIMESTAMPS) && REGION_SIZE(pcie_timestamp) > 0) {
+		uint64_t pre_timestamp, cur_timestamp, perst_time;
+
+		pre_timestamp = read64(_pcie_timestamp);
+		cur_timestamp = timestamp_get();
+		perst_time = cur_timestamp - pre_timestamp;
+
+		printk(BIOS_DEBUG, "%s: [%lld] us elapsed since assert PERST#\n",
+		       __func__, perst_time);
+
+		/*
+		 * Described in PCIe CEM specification sections 2.2
+		 * (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)).
+		 * The deassertion of PERST# should be delayed 100ms (TPVPERL)
+		 * for the power and clock to become stable.
+		 */
+		if (perst_time < 100000)
+			printk(BIOS_WARNING, "%s: PERST# assert time [%lld] us may not enough for link up\n",
+			       __func__, perst_time);
+	}
+
    /* De-assert reset signals */
    mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, false);