[coreboot-gerrit] [M] Change in coreboot[master]: soc/amd/spi: Mmap 32M/64M flash

[Bao Zheng (Code Review)]

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held.

Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/74260

to look at the new patch set (#7).

Change subject: soc/amd/spi: Mmap 32M/64M flash
......................................................................

soc/amd/spi: Mmap 32M/64M flash

For the flash size bigger than 16M, AMD SOC maps only one 16M page at
a time and use SPI ROM page register to switch pages. We let CBFS and
flashmap access the physical SPI device not being aware the existence
of the switcher.

We need to switch back to page 0 in munmap because the FSP relies on
this fact.

This is one of series of patches to support 32/64M flash. The most
important one.
BUG=b:255374782

Change-Id: Ibd2bf1390635494443cac9ee8600a4a741a78c0d
Signed-off-by: Zheng Bao 
---
M src/soc/amd/common/block/lpc/Kconfig
M src/soc/amd/common/block/lpc/Makefile.inc
A src/soc/amd/common/block/lpc/spi_map_big.c
3 files changed, 119 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/74260/7