Attention is currently required from: Nick Vaccaro, Subrata Banik.
Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79920?usp=email )
Change subject: soc/intel/tigerlake: Drop redundant PcieRpEnable ......................................................................
soc/intel/tigerlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infracture instead.
Note: Jenkins will fail because somebody has to go through all the dts.
Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 5 files changed, 4 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/79920/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 1af05c4..6a7db5f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -37,10 +37,6 @@ # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901"
- register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[10]" = "1" register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index ad1a45d..5960a3c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -38,10 +38,6 @@ # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901"
- register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[10]" = "1" register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 435572e..27e07a9 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -20,6 +20,7 @@
romstage-y += espi.c romstage-y += meminit.c +romstage-y += pcie_rp.c romstage-y += reset.c
ramstage-y += acpi.c diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 3de8ffa..8700dd5 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -258,7 +258,6 @@ uint8_t PchHdaIDispCodecDisconnect;
/* PCIe Root Ports */ - uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; /* Implemented as slot or built-in? */ uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index afcbf2f..baf2eb3 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -9,6 +9,7 @@ #include <fsp/util.h> #include <gpio.h> #include <intelblocks/cpulib.h> +#include <intelblocks/pcie_rp.h> #include <option.h> #include <soc/iomap.h> #include <soc/msr.h> @@ -21,7 +22,7 @@ const struct soc_intel_tigerlake_config *config) { unsigned int i; - uint32_t cpu_id, mask = 0; + uint32_t cpu_id;
m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING));
@@ -49,11 +50,7 @@ m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; }
- for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->PcieRpEnableMask = mask; + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(soc_get_pch_rp_groups());
memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, sizeof(config->PcieClkSrcUsage));