Amanda Hwang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
Patch Set 10:
(8 comments)
https://review.coreboot.org/c/coreboot/+/38399/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/1/src/mainboard/google/hatch/... PS1, Line 66:
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https://review.coreboot.org/c/coreboot/+/38399/1/src/mainboard/google/hatch/... PS1, Line 74:
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https://review.coreboot.org/c/coreboot/+/38399/1/src/mainboard/google/hatch/... PS1, Line 81:
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https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... PS5, Line 75: # PCIe port 3 reserve for GPU REFCLK : register "PcieRpEnable[2]" = "1" : register "PcieRpLtrEnable[2]" = "
PCIE#3 seems to be connected to test points? […]
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https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... PS5, Line 80: 2
Updated as patch set 6.
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https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... PS5, Line 74: : # PCIe port 3 reserve for GPU REFCLK : register "PcieRpEnable[2]" = "1" : register "PcieRpLtrEnable[2]" = "1" : # RP 3 uses CLK SRC 2 : register "PcieClkSrcUsage[2]" = "2" : register "PcieClkSrcClkReq[2]" = "2"
Sorry, updating the last comment. […]
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https://review.coreboot.org/c/coreboot/+/38399/7/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/7/src/mainboard/google/hatch/... PS7, Line 66:
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https://review.coreboot.org/c/coreboot/+/38399/7/src/mainboard/google/hatch/... PS7, Line 73:
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