[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Move `gpi_clear_int_cfg()` call

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51148 )

Change subject: soc/intel/cannonlake: Move `gpi_clear_int_cfg()` call
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soc/intel/cannonlake: Move `gpi_clear_int_cfg()` call

To allow unifying bootblock.c in follow-ups, move a function call.

Change-Id: I0f40ee7fd47f7f9f582f314dfcd1b4b93b1db791
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51148
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Furquan Shaikh 
---
M src/soc/intel/cannonlake/bootblock/bootblock.c
M src/soc/intel/cannonlake/bootblock/pch.c
2 files changed, 7 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
index dfa0bd0..1354c43 100644
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -61,11 +61,6 @@

void bootblock_soc_init(void)
 {
-	/*
-	 * Clear the GPI interrupt status and enable registers. These
-	 * registers do not get reset to default state when booting from S5.
-	 */
-	gpi_clear_int_cfg();
    report_platform_info();
    bootblock_pch_init();

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 51f8fb5..a4f47c9 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -6,6 +6,7 @@
 #include <device/pci_ops.h>
 #include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
+#include <intelblocks/gpio.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/p2sb.h>
@@ -132,6 +133,12 @@
 void bootblock_pch_init(void)
 {
    /*
+	 * Clear the GPI interrupt status and enable registers. These
+	 * registers do not get reset to default state when booting from S5.
+	 */
+	gpi_clear_int_cfg();
+
+	/*
     * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
     * GPE0_STS, GPE0_EN registers.
     */