Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13992
-gerrit
commit 064caa68fbba77813604793e4efa27c06a05258c Author: Naresh G Solanki naresh.solanki@intel.com Date: Mon Feb 29 13:20:44 2016 +0530
skylake mainboards: Configure gpio PADRSTCFG to PLTRST
With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over pltrst and hence configuring PADRSTCFG to PLTRST to prevent IRQ strom after S3 resume.
BRANCH=glados BUG=chrome-os-partner:50536 TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed after S3 resume.
Change-Id: I7f1ae90aed03778e7d6cb2d79de0efe9a6d9e20d Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: aff91da4feaf8f7e42cfeee756cf468288cbfd68 Original-Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac Original-Signed-off-by: Naresh G Solanki naresh.solanki@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/329453 Original-Commit-Ready: Naresh Solanki naresh.solanki@intel.com Original-Tested-by: Naresh Solanki naresh.solanki@intel.com Original-Reviewed-by: Duncan Laurie dlaurie@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/331174 Original-Commit-Ready: Patrick Georgi pgeorgi@chromium.org Original-Tested-by: Patrick Georgi pgeorgi@chromium.org --- src/mainboard/google/chell/gpio.h | 8 +++--- src/mainboard/google/lars/gpio.h | 48 ++++++++++++++++++------------------ src/mainboard/intel/kunimitsu/gpio.h | 10 ++++---- 3 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index 0503e3e..05897eb 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP), /* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), /* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD_INT_L */ +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD_INT_L */ /* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ @@ -155,14 +155,14 @@ static const struct pad_config gpio_table[] = { /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), /* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN_INT_L */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ /* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ /* USB2_OC1# */ PAD_CFG_NC(GPP_E10), @@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ PAD_CFG_NC(GPP_F7), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ /* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h index 5aee237..e187795 100644 --- a/src/mainboard/google/lars/gpio.h +++ b/src/mainboard/google/lars/gpio.h @@ -72,19 +72,19 @@ static const struct pad_config gpio_table[] = { /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ /* GPP_A16 */ -/* SD_PWR_EN */ /* GPP_A17 */ -/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), -/* ISH_GP1 */ /* GPP_A19 */ -/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), -/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), -/* GYRO_INT */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), -/* ISH_GP5 */ /* GPP_A23 */ -/* CORE_VID0 */ /* GPP_B0 */ -/* CORE_VID1 */ /* GPP_B1 */ -/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), -/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17), +/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), +/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), +/* GYRO_INT */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* HSJ_MIC_DET */ PAD_CFG_GPO(GPP_B2, 0, DEEP), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), @@ -152,15 +152,15 @@ static const struct pad_config gpio_table[] = { /* ITCH_SPI_D2 */ /* GPP_D21 */ /* ITCH_SPI_D3 */ /* GPP_D22 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), -/* SATAXPCIE1 */ /* GPP_E1 */ -/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), -/* CPU_GP0 */ /* GPP_E3 */ -/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), -/* SATA_DEVSLP1 */ /* GPP_E5 */ -/* SATA_DEVSLP2 */ /* GPP_E6 */ -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), -/* SATALED# */ /* GPP_E8 */ +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), +/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), +/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), +/* TCH_PNL_INTR* */ PAD_CFG_NC(GPP_E7), +/* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), @@ -186,8 +186,8 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ /* GPP_F7 */ /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), -/* I2C5_SCL */ /* GPP_F11 */ +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), +/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index de51fb5..d310396 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), @@ -160,14 +160,14 @@ static const struct pad_config gpio_table[] = { /* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), /* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), /* SSD_PEDET */ PAD_CFG_NC(GPP_E2), /* AUDIO_DB_ID */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), @@ -181,7 +181,7 @@ static const struct pad_config gpio_table[] = { /* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), @@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ PAD_CFG_NC(GPP_F7), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),