[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8192: Keep CONN MCU in reset state

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46447 )

Change subject: soc/mediatek/mt8192: Keep CONN MCU in reset state
......................................................................

soc/mediatek/mt8192: Keep CONN MCU in reset state

Keep the CONN MCU in reset state to prevent CONN from asserting the
clk26m request to SPM.

TEST=clk26m request from conn has been released.

Signed-off-by: Weiyi Lu 
Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46447
Tested-by: build bot (Jenkins) 
Reviewed-by: Hung-Te Lin 
Reviewed-by: Yu-Ping Wu 
---
M src/soc/mediatek/mt8192/include/soc/pll.h
M src/soc/mediatek/mt8192/pll.c
2 files changed, 9 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Hung-Te Lin: Looks good to me, approved
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h
index 170196b..52bf3c2 100644
--- a/src/soc/mediatek/mt8192/include/soc/pll.h
+++ b/src/soc/mediatek/mt8192/include/soc/pll.h
@@ -306,6 +306,9 @@
 DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4)
 DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16)

+DEFINE_BITFIELD(WDT_SWSYSRST_KEY, 31, 24)
+DEFINE_BITFIELD(WDT_SWSYSRST_CONN_MCU, 12, 12)
+
 enum {
    INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = (0x1f << 12) | (0x1 << 17) | (0x1 << 18),
    INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = (0x10 << 12) | (0x1 << 17) | (0x0 << 18),
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index afa7c85..6d61fb4 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -10,6 +10,7 @@
 #include <soc/infracfg.h>
 #include <soc/mcucfg.h>
 #include <soc/pll.h>
+#include <soc/wdt.h>

enum mux_id {
    TOP_AXI_SEL,
@@ -467,6 +468,11 @@

/* enable [14] dramc_pll104m_ck */
    setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
+
+	/* reset CONNSYS MCU */
+	SET32_BITFIELDS(&mtk_wdt->wdt_swsysrst,
+			WDT_SWSYSRST_KEY, 0x88,
+			WDT_SWSYSRST_CONN_MCU, 0x1);
 }

void mt_pll_raise_little_cpu_freq(u32 freq)