Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph.
Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/86584?usp=email
to look at the new patch set (#2).
Change subject: soc/amd/common/block/lpc: Use ROM3 window if possible ......................................................................
soc/amd/common/block/lpc: Use ROM3 window if possible
On x86_64 use the ROM3 window to access the SPI flash. Use the same mechanism as on Intel, where the lower 16Mbyte are mapped using ROM2 window and the upper pages are mapped using the ROM3 window. By default the ROM3 window resides in high MMIO and thus needs 1024GiB of the address space to be identity mapped in the page tables.
On x86_32 still only 16 MiB of the SPI flash can be mapped using the ROM2 MMIO space.
This allows legacy 32-bit code to work on mappings in the lower 16MiB of the flash chip.
Introduces new messages in coreboot log: [INFO ] ROM2 Decode Window: SPI flash base=0x0, Host base=0xff000000, Size=0x1000000 [INFO ] ROM3 Decode Window: SPI flash base=0x1000000, Host base=0xfd01000000, Size=0x3000000
TEST: Disabled ROM2 mapping and booted from ROM3 mapping in x86_64 on amd/birman+.
Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/common/block/spi/Makefile.mk A src/soc/amd/common/block/spi/mmap_boot_rom3.c M src/soc/amd/glinda/Kconfig 4 files changed, 187 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/86584/2