Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30774
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
mb/google/hatch: Configure miscellaneous features
set SaGv = 3 , To set System Agent dynamic frequency support as FixedHigh set HeciEnabled = 1, To Enable heci communication set VmxEnable = 1, To Enable Virtual-Machine Extension support set speed_shift_enable = 1 To Enable Speed Shift Technology support set s0ix_enable = 0, To Disable active idle state support. Will make it Enable when platform will be in stable stage set dptf_enable = 0, To Disable Dynamic Platform Thermal Framework support. Will make it Enable when platform will be in stable stage set dmipwroptimize = 1 , To Enable DMI Power Optimizer on PCH side
Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30774/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 45e8421..7104fd4 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -49,6 +49,13 @@ register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" register "satapwroptimize" = "1" + register "SaGv" = "3" + register "HeciEnabled" = "1" + register "VmxEnable" = "1" + register "speed_shift_enable" = "1" + register "s0ix_enable" = "0" + register "dptf_enable" = "0" + register "dmipwroptimize" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1