[coreboot-gerrit] Change in coreboot[master]: treewide: Configure PCI Bus Master based on Kconfig option

[Felix Singer (Code Review)]

Hello build bot (Jenkins), Nico Huber, Damien Zammit, David Guckian, Vanessa Eusebio, Angel Pons, Michael Niewöhner, Andrey Petrov, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42460

to look at the new patch set (#15).

Change subject: treewide: Configure PCI Bus Master based on Kconfig option
......................................................................

treewide: Configure PCI Bus Master based on Kconfig option

Change-Id: I25565315a5ddf8d53097ac4cb4884ecebcc9c0a9
Signed-off-by: Felix Singer 
---
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/gm45/iommu.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/ironlake/early_init.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/stoneyridge/psp.c
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/broadwell/adsp.c
M src/soc/intel/broadwell/hda.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/broadwell/sata.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/gspi/gspi.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/scs/early_mmc.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/denverton_ns/bootblock/uart.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/elkhartlake/bootblock/pch.c
M src/soc/intel/icelake/bootblock/pch.c
M src/soc/intel/jasperlake/bootblock/pch.c
M src/soc/intel/tigerlake/bootblock/pch.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/early_usb_mrc.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me_common.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smihandler.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/early_usb.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
85 files changed, 168 insertions(+), 125 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/42460/15