[coreboot-gerrit] Change in coreboot[master]: mb/tgl: Enable SaGv for TGL-UP3 RVP

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43276 )

Change subject: mb/tgl: Enable SaGv for TGL-UP3 RVP
......................................................................

mb/tgl: Enable SaGv for TGL-UP3 RVP

BUG=none
BRANCH=none
TEST=Build and boot TGL-UP3 RVP with QS silicon successfully.

Change-Id: I5b84457a1455edfe500ce80ba7f7ca6ccce43666
Signed-off-by: Shreesh Chhabbi 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43276
Reviewed-by: Angel Pons 
Reviewed-by: Nick Vaccaro 
Reviewed-by: Wonkyu Kim 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve
  Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 5d4d246..2dd65c4 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -13,7 +13,7 @@
    register "pmc_gpe0_dw2" = "GPP_E"

# FSP configuration
-	register "SaGv" = "SaGv_Disabled"
+	register "SaGv" = "SaGv_Enabled"
    register "SmbusEnable" = "1"

register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1