Ronald G. Minnich (rminnich@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7065
-gerrit
commit 9be7a1b0845a54ec36d7997000ae721d18aa6352 Author: Ronald G. Minnich rminnich@gmail.com Date: Thu Oct 16 10:49:52 2014 +0000
RISCV: initial pass
I need to get this up as is as my SSD is dying.
Change-Id: Ie06c63db252babf4fd4b3df00fff8f5fdfc81c12 Signed-off-by: Ronald G. Minnich rminnich@gmail.com --- Makefile.inc | 5 +- src/Kconfig | 16 ++++ src/arch/riscv/Kconfig | 26 ++++++ src/arch/riscv/Makefile.inc | 96 +++++++++++++++++++++++ src/arch/riscv/bootblock.S | 64 +++++++++++++++ src/arch/riscv/bootblock_simple.c | 73 +++++++++++++++++ src/arch/riscv/id.S | 20 +++++ src/arch/riscv/id.inc | 18 +++++ src/arch/riscv/id.lds | 6 ++ src/arch/riscv/include/arch/byteorder.h | 27 +++++++ src/arch/riscv/include/arch/early_variables.h | 35 +++++++++ src/arch/riscv/include/arch/hlt.h | 6 ++ src/arch/riscv/include/arch/io.h | 35 +++++++++ src/arch/riscv/include/arch/stages.h | 29 +++++++ src/arch/riscv/include/stdint.h | 60 ++++++++++++++ src/arch/riscv/prologue.inc | 22 ++++++ src/arch/riscv/romstage.ld | 54 +++++++++++++ src/arch/riscv/stages.c | 52 ++++++++++++ src/cpu/ucb/riscv/riscv.lds | 29 +++++++ src/mainboard/emulation/Kconfig | 4 + src/mainboard/emulation/qemu-riscv/Kconfig | 92 ++++++++++++++++++++++ src/mainboard/emulation/qemu-riscv/Makefile.inc | 16 ++++ src/mainboard/emulation/qemu-riscv/board_info.txt | 2 + src/mainboard/emulation/qemu-riscv/devicetree.cb | 19 +++++ src/mainboard/emulation/qemu-riscv/mainboard.c | 26 ++++++ src/mainboard/emulation/qemu-riscv/romstage.c | 29 +++++++ src/soc/Kconfig | 1 + src/soc/Makefile.inc | 1 + src/soc/ucb/Kconfig | 1 + src/soc/ucb/Makefile.inc | 1 + src/soc/ucb/riscv/Kconfig | 77 ++++++++++++++++++ toolchain.inc | 1 + 32 files changed, 942 insertions(+), 1 deletion(-)
diff --git a/Makefile.inc b/Makefile.inc index daf4cf4..f1ee12b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -68,7 +68,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs subdirs-y := src/lib src/console src/device src/ec src/southbridge src/soc subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool -subdirs-y += src/arch/arm src/arch/arm64 src/arch/x86 +subdirs-y += src/arch/arm src/arch/arm64 src/arch/x86 src/arch/riscv subdirs-y += src/mainboard/$(MAINBOARDDIR)
subdirs-y += site-local @@ -571,6 +571,9 @@ endif ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) ROMSTAGE_ELF := romstage.elf endif +ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) +ROMSTAGE_ELF := romstage.elf +endif ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) ROMSTAGE_ELF := romstage_xip.elf endif diff --git a/src/Kconfig b/src/Kconfig index ecdc929..4c03228 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -218,9 +218,14 @@ config ARCH_ARM64 bool default n
+config ARCH_RISCV + bool + default n + source src/arch/x86/Kconfig source src/arch/arm/Kconfig source src/arch/arm64/Kconfig +source src/arch/riscv/Kconfig
source src/vendorcode/Kconfig
@@ -438,6 +443,8 @@ config HAVE_ACPI_TABLES help This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. + Whether or not the ACPI tables are actually generated by coreboot + is configurable by the user via GENERATE_ACPI_TABLES.
config HAVE_MP_TABLE bool @@ -475,6 +482,15 @@ config PER_DEVICE_ACPI_TABLES
menu "System tables"
+config GENERATE_ACPI_TABLES + prompt "Generate ACPI tables" if HAVE_ACPI_TABLES + bool + default HAVE_ACPI_TABLES + help + Generate ACPI tables for this board. + + If unsure, say Y. + config GENERATE_MP_TABLE prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC bool diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig new file mode 100644 index 0000000..120203d --- /dev/null +++ b/src/arch/riscv/Kconfig @@ -0,0 +1,26 @@ +config ARCH_BOOTBLOCK_RISCV + bool + default n + select ARCH_RISCV + +config ARCH_ROMSTAGE_RISCV + bool + default n + +config ARCH_RAMSTAGE_RISCV + bool + default n + +# If a custom bootblock is necessary, this option should be "select"-ed by +# the thing that needs it, probably the CPU. +config RISCV_BOOTBLOCK_CUSTOM + bool + default n + +config CPU_HAS_BOOTBLOCK_INIT + bool + default n + +config MAINBOARD_HAS_BOOTBLOCK_INIT + bool + default n diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc new file mode 100644 index 0000000..3e5289d --- /dev/null +++ b/src/arch/riscv/Makefile.inc @@ -0,0 +1,96 @@ +################################################################################ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 The ChromiumOS Authors +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +################################################################################ + +riscv_flags = -march=elf64-littleriscv -I$(src)/arch/riscv/ + +riscv_asm_flags = $(riscv_flags) + +################################################################################ +## bootblock +################################################################################ +ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y) + +bootblock_lds += $(src)/arch/riscv/id.lds + +bootblock_inc += $(src)/arch/riscv/id.inc + +$(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions + @printf " GEN $(subst $(obj)/,,$(@))\n" + printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ + +$(objgenerated)/bootblock_inc.S: $$(bootblock_inc) + @printf " GEN $(subst $(obj)/,,$(@))\n" + printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ + +$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC_bootblock) $(CFLAGS_riscv) $(DISASSEMBLY) -c -o $@ $< > $(basename $@).disasm + +$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ + +$(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) + @printf " ROMCC $(subst $(obj)/,,$(@))\n" + $(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ + $< > $(objgenerated)/bootblock.inc.d + $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ + +$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld + @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD_bootblock) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld +else + $(CC_bootblock) $(CFLAGS_bootblock) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< +endif + +endif + +################################################################################ +## romstage +################################################################################ +ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) + +romstage-y += stages.c +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c + +# Build the romstage + +$(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/riscv/romstage.ld $(obj)/ldoptions + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(CC_romstage) $(CFLAGS_romstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/riscv/romstage.ld -Wl,--start-group $(romstage-objs) -Wl,--end-group + +romstage-c-ccopts += $(riscv_flags) +romstage-S-ccopts += $(riscv_asm_flags) + +CBFSTOOL_PRE1_OPTS = -m riscv -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET) + +endif + +################################################################################ +## ramstage +################################################################################ +ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) + +ramstage-c-ccopts += $(riscv_flags) +ramstage-S-ccopts += $(riscv_asm_flags) + +endif diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S new file mode 100644 index 0000000..73826cb --- /dev/null +++ b/src/arch/riscv/bootblock.S @@ -0,0 +1,64 @@ +/* + * Early initialization code for aarch64 (a.k.a. armv8) + * + * Copyright 2013Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.section ".start", "a", %progbits +.globl _start +_start: + .balignl 16,0xdeadbeef + +_cbfs_master_header: + /* The CBFS master header is inserted by cbfstool at the first + * aligned offset after the above anchor string is found. + * Hence, we leave some space for it. + * Assumes 64-byte alignment. + */ + .skip 128 + +reset: +init_stack_loop: + +/* Set stackpointer in internal RAM to call bootblock main() */ +call_bootblock: + +.align 3 +.Stack: + .word CONFIG_STACK_TOP +.align 3 +.Stack_size: + .word CONFIG_STACK_SIZE + .section ".id", "a", %progbits + + .globl __id_start +__id_start: +ver: + .asciz COREBOOT_VERSION +vendor: + .asciz CONFIG_MAINBOARD_VENDOR +part: + .asciz CONFIG_MAINBOARD_PART_NUMBER +.long __id_end - ver/* Reverse offset to the vendor id */ +.long __id_end - vendor/* Reverse offset to the vendor id */ +.long __id_end - part /* Reverse offset to the part number */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ + .globl __id_end + +__id_end: +.previous diff --git a/src/arch/riscv/bootblock_simple.c b/src/arch/riscv/bootblock_simple.c new file mode 100644 index 0000000..d8339d1 --- /dev/null +++ b/src/arch/riscv/bootblock_simple.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <bootblock_common.h> +#include <arch/cache.h> +#include <arch/hlt.h> +#include <arch/stages.h> +#include <arch/exception.h> +#include <cbfs.h> +#include <console/console.h> + +static int boot_cpu(void) +{ + /* + * FIXME: This is a stub for now. All non-boot CPUs should be + * waiting for an interrupt. We could move the chunk of assembly + * which puts them to sleep in here... + */ + return 1; +} + +void main(void) +{ + const char *stage_name = CONFIG_CBFS_PREFIX"/romstage"; + void *entry = NULL; + + /* Globally disable MMU, caches, and branch prediction (these should + * be disabled by default on reset) */ + dcache_mmu_disable(); + + /* + * Re-enable icache and branch prediction. MMU and dcache will be + * set up later. + * + * Note: If booting from USB, we need to disable branch prediction + * before copying from USB into RAM (FIXME: why?) + */ + + if (boot_cpu()) { + //bootblock_cpu_init(); + //bootblock_mainboard_init(); + } + +#ifdef CONFIG_BOOTBLOCK_CONSOLE + console_init(); + exception_init(); +#endif + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); + + printk(BIOS_SPEW, "stage_name %s, entry %p\n", stage_name, entry); + + if (entry) stage_exit(entry); + hlt(); +} diff --git a/src/arch/riscv/id.S b/src/arch/riscv/id.S new file mode 100644 index 0000000..a588f1e --- /dev/null +++ b/src/arch/riscv/id.S @@ -0,0 +1,20 @@ +#include <build.h> + + .section ".id", "a", %progbits + + .globl __id_start +__id_start: +ver: + .asciz COREBOOT_VERSION +vendor: + .asciz CONFIG_MAINBOARD_VENDOR +part: + .asciz CONFIG_MAINBOARD_PART_NUMBER +.long __id_end - ver /* Reverse offset to the vendor id */ +.long __id_end - vendor /* Reverse offset to the vendor id */ +.long __id_end - part /* Reverse offset to the part number */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ + .globl __id_end + +__id_end: +.previous diff --git a/src/arch/riscv/id.inc b/src/arch/riscv/id.inc new file mode 100644 index 0000000..f8aba0b --- /dev/null +++ b/src/arch/riscv/id.inc @@ -0,0 +1,18 @@ + .section ".id", "a", @progbits + + .globl __id_start +__id_start: +ver: + .asciz COREBOOT_VERSION +vendor: + .asciz CONFIG_MAINBOARD_VENDOR +part: + .asciz CONFIG_MAINBOARD_PART_NUMBER +.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the vendor id */ +.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */ +.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ + .globl __id_end + +__id_end: +.previous diff --git a/src/arch/riscv/id.lds b/src/arch/riscv/id.lds new file mode 100644 index 0000000..cfd091d --- /dev/null +++ b/src/arch/riscv/id.lds @@ -0,0 +1,6 @@ +SECTIONS { + . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; + .id (.): { + *(.id) + } +} diff --git a/src/arch/riscv/include/arch/byteorder.h b/src/arch/riscv/include/arch/byteorder.h new file mode 100644 index 0000000..8dc069f --- /dev/null +++ b/src/arch/riscv/include/arch/byteorder.h @@ -0,0 +1,27 @@ +#ifndef _BYTEORDER_H +#define _BYTEORDER_H + +#define __LITTLE_ENDIAN 1234 + +#include <stdint.h> +#include <swab.h> + +#define cpu_to_le64(x) ((uint64_t)(x)) +#define le64_to_cpu(x) ((uint64_t)(x)) +#define cpu_to_le32(x) ((uint32_t)(x)) +#define le32_to_cpu(x) ((uint32_t)(x)) +#define cpu_to_le16(x) ((uint16_t)(x)) +#define le16_to_cpu(x) ((uint16_t)(x)) +#define cpu_to_be64(x) swab64(x) +#define be64_to_cpu(x) swab64(x) +#define cpu_to_be32(x) swab32((x)) +#define be32_to_cpu(x) swab32((x)) +#define cpu_to_be16(x) swab16((x)) +#define be16_to_cpu(x) swab16((x)) + +#define ntohll(x) be64_to_cpu(x) +#define htonll(x) cpu_to_be64(x) +#define ntohl(x) be32_to_cpu(x) +#define htonl(x) cpu_to_be32(x) + +#endif /* _BYTEORDER_H */ diff --git a/src/arch/riscv/include/arch/early_variables.h b/src/arch/riscv/include/arch/early_variables.h new file mode 100644 index 0000000..3a1f20d --- /dev/null +++ b/src/arch/riscv/include/arch/early_variables.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef ARCH_EARLY_VARIABLES_H +#define ARCH_EARLY_VARIABLES_H + +#if defined(CONFIG_CAR_MIGRATION) && CONFIG_CAR_MIGRATION + #error "This is RISCV, silly... we don't have CAR here." +#endif + +#define CAR_GLOBAL + +#define CAR_MIGRATE(migrate_fn_) +static inline void *car_get_var_ptr(void *var) { return var; } +#define car_get_var(var) (var) +#define car_set_var(var, val) do { (var) = (val); } while (0) +static inline void car_migrate_variables(void) { } + +#endif diff --git a/src/arch/riscv/include/arch/hlt.h b/src/arch/riscv/include/arch/hlt.h new file mode 100644 index 0000000..12099a9 --- /dev/null +++ b/src/arch/riscv/include/arch/hlt.h @@ -0,0 +1,6 @@ +static inline __attribute__((always_inline)) void hlt(void) +{ + while(1); +} + + diff --git a/src/arch/riscv/include/arch/io.h b/src/arch/riscv/include/arch/io.h new file mode 100644 index 0000000..1890925 --- /dev/null +++ b/src/arch/riscv/include/arch/io.h @@ -0,0 +1,35 @@ +#ifndef _ASM_IO_H +#define _ASM_IO_H + +#include <stdint.h> + +static inline void outb(uint8_t value, uint16_t port) +{ +} + +static inline void outw(uint16_t value, uint16_t port) +{ +} + +static inline void outl(uint32_t value, uint16_t port) +{ +} + + +static inline uint8_t inb(uint16_t port) +{ + return 0; +} + + +static inline uint16_t inw(uint16_t port) +{ + return 0; +} + +static inline uint32_t inl(uint16_t port) +{ + return 0; +} + +#endif diff --git a/src/arch/riscv/include/arch/stages.h b/src/arch/riscv/include/arch/stages.h new file mode 100644 index 0000000..2d1192a --- /dev/null +++ b/src/arch/riscv/include/arch/stages.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 The ChromiumOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ARCH_STAGES_H +#define __ARCH_STAGES_H + +extern void main(void); + +void stage_entry(void) __attribute__((section(".text.stage_entry.riscv"))); +void stage_exit(void *); +void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); + +#endif diff --git a/src/arch/riscv/include/stdint.h b/src/arch/riscv/include/stdint.h new file mode 100644 index 0000000..a14d053 --- /dev/null +++ b/src/arch/riscv/include/stdint.h @@ -0,0 +1,60 @@ +#ifndef RISCV_STDINT_H +#define RISCV_STDINT_H + +/* Exact integral types */ +typedef unsigned char uint8_t; +typedef signed char int8_t; + +typedef unsigned short uint16_t; +typedef signed short int16_t; + +typedef unsigned int uint32_t; +typedef signed int int32_t; + +typedef unsigned long long uint64_t; +typedef signed long long int64_t; + +/* Small types */ +typedef unsigned char uint_least8_t; +typedef signed char int_least8_t; + +typedef unsigned short uint_least16_t; +typedef signed short int_least16_t; + +typedef unsigned int uint_least32_t; +typedef signed int int_least32_t; + +typedef unsigned long long uint_least64_t; +typedef signed long long int_least64_t; + +/* Fast Types */ +typedef unsigned char uint_fast8_t; +typedef signed char int_fast8_t; + +typedef unsigned int uint_fast16_t; +typedef signed int int_fast16_t; + +typedef unsigned int uint_fast32_t; +typedef signed int int_fast32_t; + +typedef unsigned long long uint_fast64_t; +typedef signed long long int_fast64_t; + +typedef long long int intmax_t; +typedef unsigned long long uintmax_t; + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; + + +/* Types for `void *' pointers. */ +typedef s64 intptr_t; +typedef u64 uintptr_t; + +#endif /* RISCV_STDINT_H */ diff --git a/src/arch/riscv/prologue.inc b/src/arch/riscv/prologue.inc new file mode 100644 index 0000000..8cf67c0 --- /dev/null +++ b/src/arch/riscv/prologue.inc @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Eric Biederman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +.section ".rom.data", "a", @progbits +.section ".rom.text", "ax", @progbits + diff --git a/src/arch/riscv/romstage.ld b/src/arch/riscv/romstage.ld new file mode 100644 index 0000000..1bd0fff --- /dev/null +++ b/src/arch/riscv/romstage.ld @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") +OUTPUT_ARCH(riscv) + +TARGET(binary) +SECTIONS +{ + . = 0 /*ROMSTAGE_BASE*/; + + .rom . : { + _rom = .; + *(.rom.text); + *(.rom.data); + *(.rodata); + *(.rodata.*); + *(.rom.data.*); + . = ALIGN(16); + _car_migrate_start = .; + *(.car.migrate); + LONG(0); + _car_migrate_end = .; + . = ALIGN(16); + _erom = .; + } + + /DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.eh_frame); + } + +} diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/stages.c new file mode 100644 index 0000000..570ba9e --- /dev/null +++ b/src/arch/riscv/stages.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * This file contains entry/exit functions for each stage during coreboot + * execution (bootblock entry and ramstage exit will depend on external + * loading). + * + * Entry points must be placed at the location the previous stage jumps + * to (the lowest address in the stage image). This is done by giving + * stage_entry() its own section in .text and placing it first in the + * linker script. + */ + +#include <arch/stages.h> + +void stage_entry(void) +{ + main(); +} + +/* we had marked 'doit' as 'noreturn'. + * There is no apparent harm in leaving it as something we can return from, and in the one + * case where we call a payload, the payload is allowed to return. + * Hence, leave it as something we can return from. + */ +void stage_exit(void *addr) +{ + void (*doit)(void) = addr; + /* + * Most stages load code so we need to sync caches here. Should maybe + * go into cbfs_load_stage() instead... + */ + //cache_sync_instructions(); + doit(); +} diff --git a/src/cpu/ucb/riscv/riscv.lds b/src/cpu/ucb/riscv/riscv.lds new file mode 100644 index 0000000..69469b9 --- /dev/null +++ b/src/cpu/ucb/riscv/riscv.lds @@ -0,0 +1,29 @@ +OUTPUT_ARCH(riscv) +ENTRY(_start) + +SECTIONS +{ + /* Beginning of code and text segment */ + . = 0x2000; + _start = 0x2000; + + .text : AT(ADDR(.text)) { + _text = .; + _stext = .; + _etext = .; + } + + /* Start of data section */ + _sdata = .; + .sdata : { + _gp = . + 0x800; + *(.sdata*) + } + .srodata : { + *(.srodata*) + } + /* End of data section */ + _edata = .; + + +} diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 3fbc415..a1ee02d 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -12,6 +12,9 @@ config BOARD_EMULATION_QEMU_X86_Q35 config BOARD_EMULATION_QEMU_ARMV7 bool "QEMU armv7 (vexpress-a9)"
+config BOARD_EMULATION_QEMU_UCB_RISCV + bool "QEMU ucb riscv" + endchoice
config BOARD_EMULATION_QEMU_X86 @@ -22,6 +25,7 @@ config BOARD_EMULATION_QEMU_X86 source "src/mainboard/emulation/qemu-i440fx/Kconfig" source "src/mainboard/emulation/qemu-q35/Kconfig" source "src/mainboard/emulation/qemu-armv7/Kconfig" +source "src/mainboard/emulation/qemu-riscv/Kconfig"
config MAINBOARD_VENDOR string diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig new file mode 100644 index 0000000..339c694 --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -0,0 +1,92 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +# To execute, do: +# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom + +if BOARD_EMULATION_QEMU_UCB_RISCV + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_UCB_RISCV + select BOARD_ROMSIZE_KB_4096 + select ARCH_BOOTBLOCK_RISCV + +config MAINBOARD_DIR + string + default emulation/qemu-riscv + +config MAINBOARD_PART_NUMBER + string + default "QEMU RISCV" + +config MAX_CPUS + int + default 1 + +config MAINBOARD_VENDOR + string + default "UCB" + +config DRAM_SIZE_MB + int + default 1024 + +# Memory map for qemu riscv +# +# 0x0000_0000: jump instruction (by qemu) +# 0x0002_0000: bootblock (entry of kernel / firmware) +# 0x0003_0000: romstage, assume up to 128KB in size. +# 0x0007_ff00: stack pointer +# 0x0010_0000: CBFS header +# 0x0011_0000: CBFS data +# 0x0100_0000: reserved for ramstage + +config BOOTBLOCK_BASE + hex + default 0x00002000 + +config ROMSTAGE_BASE + hex + default 0x00020000 + +config RAMSTAGE_BASE + hex + default SYS_SDRAM_BASE + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex + default 0x0100000 + +config CBFS_ROM_OFFSET + hex + default 0x0110000 + +config STACK_TOP + hex + default 0x0007ff00 + +config STACK_BOTTOM + hex + default 0x00040000 + +config STACK_SIZE + hex + default 0x0003ff00 + +endif # BOARD_EMULATION_QEMU_UCB_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc new file mode 100644 index 0000000..1530707 --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +romstage-y += romstage.c + diff --git a/src/mainboard/emulation/qemu-riscv/board_info.txt b/src/mainboard/emulation/qemu-riscv/board_info.txt new file mode 100644 index 0000000..811e8e0 --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/board_info.txt @@ -0,0 +1,2 @@ +Board name: QEMU RISCV +Category: emulation diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv/devicetree.cb new file mode 100644 index 0000000..c32cc59 --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/devicetree.cb @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google, Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +chip soc/ucb/riscv + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c new file mode 100644 index 0000000..e75ea4e --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> + +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Enable qemu/riscv device...\n"); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/emulation/qemu-riscv/romstage.c b/src/mainboard/emulation/qemu-riscv/romstage.c new file mode 100644 index 0000000..00dfecd --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/romstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <arch/stages.h> + +void main(void) +{ + void *entry; + + console_init(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + + stage_exit(entry); +} diff --git a/src/soc/Kconfig b/src/soc/Kconfig index 53d7b90..0412919 100644 --- a/src/soc/Kconfig +++ b/src/soc/Kconfig @@ -2,3 +2,4 @@ source src/soc/intel/Kconfig source src/soc/nvidia/Kconfig source src/soc/qualcomm/Kconfig source src/soc/samsung/Kconfig +source src/soc/ucb/Kconfig diff --git a/src/soc/Makefile.inc b/src/soc/Makefile.inc index 6939346..ab3e166 100644 --- a/src/soc/Makefile.inc +++ b/src/soc/Makefile.inc @@ -5,3 +5,4 @@ subdirs-y += intel subdirs-y += nvidia subdirs-y += qualcomm subdirs-y += samsung +subdirs-y += ucb diff --git a/src/soc/ucb/Kconfig b/src/soc/ucb/Kconfig new file mode 100644 index 0000000..7af50cb --- /dev/null +++ b/src/soc/ucb/Kconfig @@ -0,0 +1 @@ +source src/soc/ucb/riscv/Kconfig diff --git a/src/soc/ucb/Makefile.inc b/src/soc/ucb/Makefile.inc new file mode 100644 index 0000000..35bc728 --- /dev/null +++ b/src/soc/ucb/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_CPU_UCB_RISCV) += riscv diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig new file mode 100644 index 0000000..bc16406 --- /dev/null +++ b/src/soc/ucb/riscv/Kconfig @@ -0,0 +1,77 @@ +config SOC_UCB_RISCV + select ARCH_RISCV + select ARCH_BOOTBLOCK_RISCV + select ARCH_ROMSTAGE_RISCV + select ARCH_RAMSTAGE_RISCV + select DYNAMIC_CBMEM + bool + default n + +if SOC_UCB_RISCV + +config BOOTBLOCK_CPU_INIT + string + default "soc/ucb/riscv/bootblock.c" + help + CPU/SoC-specific bootblock code. This is useful if the + bootblock must load microcode or copy data from ROM before + searching for the bootblock. + +# ROM image layout. +# +# 0x02000 Bootblock + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x18000 + +config CBFS_ROM_OFFSET + hex "offset of CBFS data in ROM" + default 0x18080 + +config SYS_SDRAM_BASE + hex + default 0x80000000 + +config BOOTBLOCK_BASE + hex + default 0x4000e000 + +config ROMSTAGE_BASE + hex + default 0x40017000 + +config RAMSTAGE_BASE + hex + default 0x80200000 + +config STACK_TOP + hex + default 0x4000c000 + +config STACK_BOTTOM + hex + default 0x40004000 + +config STACK_SIZE + hex + default 0x800 + +# TTB needs to be aligned to 16KB. Stick it in iRAM. +config TTB_BUFFER + hex "memory address of the TTB buffer" + default 0x40000000 + +config CBFS_CACHE_ADDRESS + hex "memory address to put CBFS cache data" + default 0x40020000 + +config CBFS_CACHE_SIZE + hex "size of CBFS cache data" + default 0x00020000 + +endif diff --git a/toolchain.inc b/toolchain.inc index 2a68576..3db2957 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -57,6 +57,7 @@ ARCHDIR-i386 := x86 ARCHDIR-x86_32 := x86 ARCHDIR-arm := arm ARCHDIR-arm64 := arm64 +ARCHDIR-riscv := riscv
CFLAGS_arm := -mno-unaligned-access -ffunction-sections -fdata-sections