Hello Aamir Bohra,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/35078
to review the following change.
Change subject: Fix audio failure on drallion with FSP 1263 ......................................................................
Fix audio failure on drallion with FSP 1263
FSP 1263 looks for UPD configuration of "AudioLinkHda" if false it disables SDI# link for the codec.
Change-Id: I8330f47416e580bf6b9ca1faed1de5cd578d0e2e --- M src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 5 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/35078/1
diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb index fe3b6c9..8470a2c 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb @@ -50,6 +50,12 @@ # Enable DDC for DDI port B register "DdiPortBDdc" = "1"
+ # HDA a + register "PchHdaDspEnable" = "1" + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 575b610..8e54625 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -50,6 +50,12 @@ # Enable DDC for DDI port B register "DdiPortBDdc" = "1"
+ # HDA a + register "PchHdaDspEnable" = "1" + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index d3aab62..530d6f4 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -56,6 +56,12 @@ register "LanWakeFromDeepSx" = "0" register "WolEnableOverride" = "0"
+ # HDA a + register "PchHdaDspEnable" = "1" + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index fa98cd4..2ebe017 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -154,6 +154,7 @@
/* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ uint8_t PchHdaAudioLinkHda; + uint8_t PchHdaIDispCodecDisconnect; uint8_t PchHdaAudioLinkDmic0; uint8_t PchHdaAudioLinkDmic1; uint8_t PchHdaAudioLinkSsp0; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 494c1db..5cdddc6 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -205,6 +205,7 @@
/* Audio */ params->PchHdaDspEnable = config->PchHdaDspEnable; + params->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0; params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;