[coreboot-gerrit] Change in coreboot[master]: pciexp: retrain PCIe link at lower speed if no link

[Jonathan Kollasch (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42683

to look at the new patch set (#2).

Change subject: pciexp: retrain PCIe link at lower speed if no link
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pciexp: retrain PCIe link at lower speed if no link

Needed for PCIe x4 dual-port Marvell NIC (sky2) on Sandy/Ivy Bridge
and 6-series PCH (if not other chipsets), where the link will not come
up at 5GT/s (or 8GT/s?), but will if explicitly trained at 2.5GT/s.

Change-Id: I7ba15f7c13463356c6417f41b44d045aacfde4cc
Signed-off-by: Jonathan A. Kollasch 
---
M src/device/pciexp_device.c
M src/include/device/pci_def.h
2 files changed, 41 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/42683/2