[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: add DDR4 support

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39040 )

Change subject: soc/intel/tigerlake: add DDR4 support
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39040/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39040/3//COMMIT_MSG@9 
PS3, Line 9: Add Rcomp data structure in meminit to support updating rcomp resistor
           : and target values for DDR4 support.
> Where is the SoC code that uses this information?

Will create a function like meminit_ddr4x() in soc, currently it was done inline in fsp_params.c