Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29301
Change subject: src: Remove unneeded include <reset.h> ......................................................................
src: Remove unneeded include <reset.h>
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/arch/x86/cf9_reset.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/cpu/intel/fsp_model_406dx/bootblock.c M src/drivers/intel/fsp2_0/stage_cache.c M src/ec/google/chromeec/ec.c M src/lib/hardwaremain.c M src/mainboard/google/foster/pmic.c M src/mainboard/google/smaug/pmic.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_rialto/bootblock.c M src/mainboard/intel/stargo2/romstage.c M src/security/tpm/tspi/tspi.c M src/security/vboot/common.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/fsp_baytrail/bootblock/bootblock.c M src/soc/intel/skylake/romstage/romstage.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/sb700/early_setup.c 23 files changed, 3 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/29301/1
diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c index c28e448..d1e5704 100644 --- a/src/arch/x86/cf9_reset.c +++ b/src/arch/x86/cf9_reset.c @@ -18,7 +18,6 @@ #include <cf9_reset.h> #include <console/console.h> #include <halt.h> -#include <reset.h>
/* * A system reset in terms of the CF9 register asserts the INIT# diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 1247e60..7f441c0 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -15,6 +15,7 @@ */
#include <cpu/amd/msr.h> +#include <reset.h> #include "init_cpus.h"
#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h index d4bff0b..ddae9a6 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.h +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h @@ -23,7 +23,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> #include <cpu/amd/multicore.h> -#include <reset.h> #include <northbridge/amd/amdfam10/raminit.h> #include "defaults.h"
diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index 327c4a4..e7b017f 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -21,7 +21,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> -#include <reset.h> #include <southbridge/intel/fsp_rangeley/soc.h>
#include "model_406dx.h" diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c index 434eae9..a9ec154 100644 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <fsp/memmap.h> #include <stage_cache.h> -#include <reset.h> #include <program_loading.h>
void stage_cache_external_region(void **base, size_t *size) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 75d9da1..6efe139 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -25,7 +25,6 @@ #include <delay.h> #include <elog.h> #include <halt.h> -#include <reset.h> #include <rtc.h> #include <stdlib.h> #include <security/vboot/vboot_common.h> diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index a26d678..05164b0 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -29,7 +29,6 @@ #include <device/pci.h> #include <delay.h> #include <stdlib.h> -#include <reset.h> #include <boot/tables.h> #include <program_loading.h> #include <lib.h> diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index 8d4f855..d8b1fa0 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -20,6 +20,7 @@ #include <device/i2c_simple.h> #include <stdint.h> #include <stdlib.h> +#include <reset.h>
#include "pmic.h" #include "reset.h" diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 75075ad..a6e4574 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -20,6 +20,7 @@ #include <device/i2c_simple.h> #include <stdint.h> #include <stdlib.h> +#include <reset.h>
#include "pmic.h" #include "reset.h" diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c index 1f4eec20..a36d9b0 100644 --- a/src/mainboard/google/veyron/bootblock.c +++ b/src/mainboard/google/veyron/bootblock.c @@ -19,7 +19,6 @@ #include <bootblock_common.h> #include <console/console.h> #include <delay.h> -#include <reset.h> #include <soc/clock.h> #include <soc/i2c.h> #include <soc/grf.h> diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index b95a265..73fd544 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -19,7 +19,6 @@ #include <bootblock_common.h> #include <console/console.h> #include <delay.h> -#include <reset.h> #include <soc/clock.h> #include <soc/i2c.h> #include <soc/grf.h> diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index dae046b..474f6ec 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -19,7 +19,6 @@ #include <bootblock_common.h> #include <console/console.h> #include <delay.h> -#include <reset.h> #include <soc/clock.h> #include <soc/i2c.h> #include <soc/grf.h> diff --git a/src/mainboard/intel/stargo2/romstage.c b/src/mainboard/intel/stargo2/romstage.c index cdf087a..f5b84fd 100644 --- a/src/mainboard/intel/stargo2/romstage.c +++ b/src/mainboard/intel/stargo2/romstage.c @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <halt.h> -#include <reset.h> #include <fsp_util.h> #include <northbridge/intel/fsp_sandybridge/northbridge.h> #include <northbridge/intel/fsp_sandybridge/raminit.h> diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index d9cade9..33eaa06 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -16,7 +16,6 @@
#include <console/cbmem_console.h> #include <console/console.h> -#include <reset.h> #include <security/tpm/tspi.h> #include <security/tpm/tss.h> #include <stdlib.h> diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 72228e4..a909312 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -17,7 +17,6 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> -#include <reset.h> #include <string.h> #include <vb2_api.h> #include <security/vboot/misc.h> diff --git a/src/soc/cavium/common/bdk-coreboot.c b/src/soc/cavium/common/bdk-coreboot.c index ff30edf..b322a0c 100644 --- a/src/soc/cavium/common/bdk-coreboot.c +++ b/src/soc/cavium/common/bdk-coreboot.c @@ -23,7 +23,6 @@ #include <endian.h> #include <arch/io.h> #include <delay.h> -#include <reset.h> #include <soc/timer.h>
// BDK diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index f485dfd..17d4074 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -32,7 +32,6 @@ #include <romstage_handoff.h> #include <string.h> #include <timestamp.h> -#include <reset.h> #include <vendorcode/google/chromeos/chromeos.h> #include <fsp/util.h> #include <soc/gpio.h> diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index ebbdabd..8496536 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -24,7 +24,6 @@ #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <lib.h> -#include <reset.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/pm.h> diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index 8ce0a1d..81f5dfb 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -25,7 +25,6 @@ #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/gpio.h> -#include <reset.h>
/* * check for a warm reset and do a hard reset instead. diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 215b07c..99a8957 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -30,7 +30,6 @@ #include <elog.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pmclib.h> -#include <reset.h> #include <romstage_handoff.h> #include <soc/pci_devs.h> #include <soc/pei_wrapper.h> diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 75da9dd..cfd6d0e 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <arch/acpi.h> #include <console/console.h> -#include <reset.h> #include <arch/cpu.h> #include <cbmem.h> #include "hudson.h" diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 47d20af..cd1ff85 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -21,7 +21,6 @@ #include <arch/io.h> #include <arch/acpi.h> #include <console/console.h> -#include <reset.h> #include <arch/cpu.h> #include <cbmem.h> #include "hudson.h" diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index a656921..011a056 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -24,7 +24,6 @@ #include <console/console.h> #include <cpu/x86/msr.h>
-#include <reset.h> #include "sb700.h" #include "smbus.h"