[coreboot-gerrit] Change in ...coreboot[master]: device/pciexp_device: Add set_L1_ss_latency() for pciexp device

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31951 )

Change subject: device/pciexp_device: Add set_L1_ss_latency() for pciexp device
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Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/31951/1/src/device/pciexp_device.c 
File src/device/pciexp_device.c:

https://review.coreboot.org/#/c/31951/1/src/device/pciexp_device.c@470 
PS1, Line 470: 			PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE << 16 |
> The 'offset' parameter is found by searching a standard PCIE capability structure, so this function  […]

sorry i didn't get you. caller of this function passes offset value after reading capability ID register. this function is doing what it supposed to be, just program LTR snoop and non snoop value. what i could find my almost all code is that this value always remain same as 0x1003