[coreboot-gerrit] Change in coreboot[master]: src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL

[Ravishankar Sarawadi (Code Review)]

Ravishankar Sarawadi has uploaded a new patch set (#19) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/48286 )

Change subject: src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL
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src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL

Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config
option. Select CAR_HAS_SF_MASKS for Tigerlake.

During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x
are not being reset to default as
per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5.
Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient.

Bug=b:171601324
BRANCH=volteer
Test=Build and boot to ChromeOS on Delbin.

Signed-off-by: Shreesh Chhabbi 
Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/tigerlake/Kconfig
3 files changed, 30 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/48286/19